Joachim Strömbergson
b37b377a7e
Change optimization to Os since we want compact code
2022-10-13 09:26:49 +02:00
Michael Cardell Widerkrantz
99aabe89e9
Fix minor doc nits
2022-10-12 15:12:07 +02:00
Daniel Lublin
55c5081486
Adjust and document the firmware state-machine, including USS
...
In particular, order of LOAD_USS and LOAD_APP_SIZE is not required, but
the need to send both is documented. This is followed up with adjustment
in the host programs' Go code, to try to reinforce this. LoadApp() will
take the secretPhrase parameter (to be hashed as USS), and loadUSS()
will be unexported.
Correct CMD/RSP lengths in pseudo-code.
2022-10-12 15:12:07 +02:00
Joachim Strömbergson
5013338e50
Change to a more descriptive name
2022-10-12 11:14:46 +02:00
Joachim Strömbergson
192ce47fce
Fix #18 with incorrect clock frequency in analysis
2022-10-12 10:25:37 +02:00
Joachim Strömbergson
a9fd26da3b
Fix bit bit width mismatches
2022-10-12 10:21:50 +02:00
Joachim Strömbergson
f75860c2a2
Add link to SW page to the list of documents
...
The page is linked from the system description page,
but is probably hard to find.
2022-10-12 10:14:07 +02:00
Joachim Strömbergson
c25fc0e7f2
Fix language nits
2022-10-12 10:10:48 +02:00
Joachim Strömbergson
6ce374cd97
Merge branch 'main' of github.com:tillitis/tillitis-key1
2022-10-12 10:08:16 +02:00
Joachim Strömbergson
82a64f2b2c
Remove DONE state that added one extra final cycle
2022-10-12 10:06:41 +02:00
Daniel Lublin
200ef26f36
Correct
2022-10-11 20:46:21 +02:00
Daniel Lublin
4d927ce426
Fix size_mismatch for testfw
2022-10-11 17:25:19 +02:00
Daniel Lublin
96746b2de0
Clarify BRAM_FW_SIZE
2022-10-11 17:25:00 +02:00
Joachim Strömbergson
cbf1104fed
Write whole byte, not nybbles
2022-10-11 17:05:21 +02:00
Joachim Strömbergson
a51619e5b7
Add fw_ram module
2022-10-11 16:58:26 +02:00
Joachim Strömbergson
24cf80af32
Remove redundant spram module
2022-10-11 13:27:57 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG
2022-10-11 13:17:04 +02:00
Joachim Strömbergson
af36a40f3e
Merge branch 'new_trng'
2022-10-11 13:00:13 +02:00
Joachim Strömbergson
5087a67376
Reduce FW ROM size to 6 kByte
2022-10-11 12:54:44 +02:00
Joachim Strömbergson
4b929fedf2
Merge branch 'name_version'
2022-10-11 11:30:47 +02:00
Joachim Strömbergson
1439e4a587
Remove name, version info about cores from SW description
2022-10-11 11:28:40 +02:00
Joachim Strömbergson
87dab3fe6d
Remove name, version addresses for cores
2022-10-11 09:55:56 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores
...
timer
touch_sense
figaro
uart
uds
2022-10-11 09:50:45 +02:00
Joachim Strömbergson
cdbe71d40d
Add new ROSC based TRNG with VN decorrelation
2022-10-11 08:45:06 +02:00
Joachim Strömbergson
4ed27b4460
Add new rosc based entropy source
2022-10-08 18:37:48 +02:00
Michael Cardell Widerkrantz
df7a26c28c
Compile firmware with -DNOCONSOLE
2022-10-07 11:19:53 +02:00
Joachim Strömbergson
c90771fe19
Remove API access to current prescaler value
2022-10-06 15:56:13 +02:00
Joachim Strömbergson
cc59d8dc93
Update verilator top level module to match rom module changes
2022-10-06 13:59:01 +02:00
Joachim Strömbergson
f80aaa4e8a
Merge branch 'main' of github.com:tillitis/tillitis-key1
2022-10-06 13:25:35 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following:
...
Silence lint on intentional combinatinal loops
Use better instance names, and a single lint pragma for all macros
Remove unused pointer update signals
Silence lint on wires where not all bits are used
Change fw_app_mode to be an input port to allow access control
Remove redundant, unused wire mem_busy
Add lint pragma to ignore debug register only enabled by a define
Remove clk and reset_n ports from the ROM
Adding note and lint pragma for rom address width
Fix incorrect register widths in uart_core
Assign all 16 bits in LUT config
Silence lint warnings on macro instances
Correct bit extraction for core addresses to be eight bits wide
Correct the bit width of cdi_mem_we wire
Add specific output file for logging lint issues
Correct bit width of tmp_ready to match one bit ready port
2022-10-06 13:23:30 +02:00
Daniel Lublin
429ac6877e
Note about the importance of releases; clarify some docs
2022-10-04 13:17:37 +02:00
Daniel Lublin
2bb62af183
Update bit divisor calc in verilator's uart to our current 18 MHz
2022-10-03 13:11:53 +02:00
Joachim Strömbergson
6f31bbe37a
Merge branch 'main' of github.com:tillitis/tillitis-key1
2022-10-03 12:56:41 +02:00
Joachim Strömbergson
b2ca3f2ea0
Fix Verilator sim by adding separate reset generator
2022-10-03 12:55:24 +02:00
Daniel Lublin
0d16dd5959
Adjust flashing after frequency bump
2022-10-03 08:06:29 +02:00
Michael Cardell Widerkrantz
ffa0bb48cb
Doc: Add a warning about USS to release notes
2022-09-30 13:34:47 +02:00
Daniel Lublin
3f61182a88
Doc how qemu needs to be built; nits
2022-09-30 11:34:09 +02:00
Joachim Strömbergson
1aa2d7bd95
Merge branch 'pll'
2022-09-30 10:06:48 +02:00
Joachim Strömbergson
f41573cc60
Update bit counter to match 18 MHz clock frequency
2022-09-30 10:04:37 +02:00
Joachim Strömbergson
90dc2da8c3
Merge pull request #5 from tillitis/kicad-links
...
Fix broken links in kicad library readme
2022-09-30 08:34:53 +02:00
Daniel Lublin
fe6e7b83d1
Document need to unplug stick (and programmer)
2022-09-29 21:20:28 +02:00
Daniel Lublin
c9755e4cca
Add deps for building qemu
2022-09-29 15:24:21 +02:00
Daniel Lublin
99efb78ed8
Receive USS and hash into CDI
...
- We're OK with USS not being loaded, and use an all-zero USS if so.
- We require USS to be loaded before app_size (if at all).
2022-09-29 14:58:23 +02:00
Daniel Lublin
df67966d8f
Be consistent and check for errors first
2022-09-28 10:34:48 +02:00
Joachim Strömbergson
c0334a77da
Merge branch 'main' of github.com:tillitis/tillitis-key1
2022-09-28 10:31:00 +02:00
Joachim Strömbergson
f09ff87f9e
Support DIV instructions and catch illegal instructions
2022-09-28 10:29:00 +02:00
Daniel Lublin
34407a32ce
Update doc for revised tpt
2022-09-28 08:30:31 +02:00
Joachim Strömbergson
90a57c4948
Use PLL and global buffer to increas clock speed
2022-09-27 16:41:38 +02:00
Joachim Strömbergson
610522201b
Remove AXI and WB interface modules
2022-09-27 09:48:54 +02:00
Daniel Lublin
98c2463dbc
Reference a bit more
...
Try to make it a bit easier to understand "measure" and where to read
more.
2022-09-26 11:27:28 +02:00
