Commit Graph

516 Commits

Author SHA1 Message Date
Jonas Thörnblad
f66617431b
Update toolchain with new versions of FPGA tools and remove fw/apps/programmer toolschains
- Change docker image to ubuntu 24.04

 - Add new versions of:
	* clang (18.1.3, part of ubuntu 24.04)
	* icestorm (commit 738af822905fdcf0466e9dd784b9ae4b0b34987f)
	* yosys (0.45)
	* nextpnr (0.7) + extra patches for RNG seed handling and early exit
	* iverilog (v12)
	* verilator (v5.028)
	* verible (v0.0-3795)
	* cocotb (v1.9.1)
 - Remove:
	* gcc-arm-none-eabi
	* libnewlib-arm-none-eabi
	* libstdc++-arm-none-eabi-newlib
	* pico-sdk
	* golang
2024-10-16 18:43:29 +02:00
Jonas Thörnblad
9e57296d91
Include SPI master in default build
This prevents building without the SPI master, the intention is to use
a different method than if-defs, but it will be introduced at a later
stage.
2024-10-16 12:50:32 +02:00
Daniel Jobson
cbb2ba7512
Doc: fix typo in tk1 core readme 2024-10-11 15:50:07 +02:00
Daniel Jobson
d9d41811bd
tb: fix tk1 testbench after name change
This issue was introduced in commit 53c5e707, after name change of RAM
randomization API.
2024-10-11 15:50:07 +02:00
Daniel Jobson
056ee4d3ee
Add make target to clean testbench files
Add it as default in the contrib Makefile.
2024-10-11 15:50:07 +02:00
Daniel Jobson
f13366538e
fw: Fix erroneous type in frame header 2024-10-09 15:52:00 +02:00
Jonas Thörnblad
0ea0eeb967
Fix makefile lines and tee exit status problem
* Break long lines and use tab to indent
* Remove use of "tee" since it messes up the return status
* Remove the generated application_fpga_par.json if nextpnr-ice40 fails
  on timing.
* Change log file ending from .log to .txt
* Fix some spacing
2024-10-08 16:07:17 +02:00
Daniel Jobson
bf1ac5c237
Remove YosysHQ copyright and fix name typo
The removal is coordinated and approved by YosysHQ, and are removed
to keep our headers uniform. These files were written on behalf of
Tillitis.
Two typos was corrected as well.
2024-09-30 15:01:31 +02:00
Daniel Jobson
81950ef7b2
fw: remove warning of missing prototypes when building with QEMU console
enabled.
2024-09-19 16:52:04 +02:00
Daniel Jobson
613316f53e
fw: simplify how to enable QEMU debug in firmware.
- Remove the define `NOCONSOLE`, add define `QEMU_CONSOLE`
- Inverse the use of it, add the define to have QEMU debug output in fw.
- Add a make target `qemu_firmware.elf` which builds the firmware with
  QEMU console enabled.

Co-authored-by: Mikael Ågren <mikael@tillitis.se>
2024-09-19 16:51:55 +02:00
Joachim Strömbergson
35052e50cb
FPGA: Move RAM address and data scrambling into the RAM module.
Move the logic implementing the RAM address and data
	scrambling, descrambling into the RAM module. This cleans up
	the top level, and makes it easier to change the scrambling
	without chaning the top. In order to do correct scrambling the
	address to the RAM core must be 16 bits, not 15.

	Clean up some minor details at the top level, fixing text
        aligment and grouping of ports in instances.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-30 10:53:13 +02:00
Joachim Strömbergson
8d4ad120d6
Doc: Add README for the ROM core.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-29 16:06:59 +02:00
Joachim Strömbergson
2d769c5751
Doc: add README for the RAM.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-29 16:06:59 +02:00
Joachim Strömbergson
e2de640f01
Doc: Add README for the fw_ram.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-29 16:06:59 +02:00
Joachim Strömbergson
c9f5173c18
Doc: Add README for the clock and reset core.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-29 16:06:59 +02:00
Joachim Strömbergson
d1cff273d7
FPGA: Move all sub modules into separate cores
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-29 16:06:58 +02:00
Jonas Thörnblad
b8f22a9810
Log stdout/stderr from yosys and nextpnr-ice40 2024-08-28 14:12:10 +02:00
Joachim Strömbergson
7f93b7817b
FPGA: Add --freq constraint to nextpnr
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-20 13:45:01 +02:00
Joachim Strömbergson
75b028505f
FPGA: Increase clock frequency to 21 MHz
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-20 13:45:00 +02:00
Joachim Strömbergson
00599549e3
FPGA: Add system reset API
Add API address to trigger system reset.
      When written to will send system_reset signal
      to the reset generator, which then perform a complete
      reset cycle of the FPGA system.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-20 13:25:22 +02:00
Joachim Strömbergson
b5ba21148d
FPGA: Cleanup tk1 spi testbench
- Remove DUT variables from state display that was removed as part of
  performance fix
- Corrected some incorrect display statements for expected unique ID and
  byte counters

Co-authored-by: Daniel Jobson <jobson@tillitis.se>
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-07-11 09:39:31 +02:00
Joachim Strömbergson
4003d6a1c0
FPGA: Improve SPI testing
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-07-11 09:38:24 +02:00
Joachim Strömbergson
3d8491af71
FPGA: Move sample point to not miss MISO lsb
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-07-11 09:37:46 +02:00
Joachim Strömbergson
53c5e70795
FPGA: Update names for RAM randomization API
Update:
- README
- testbench
- Symbolic names and variables in fw
- registers
- port name and wires
- Update fpga and fw digests

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-07-10 13:45:26 +02:00
Joachim Strömbergson
816718307f
fpga: Fix nits in constant value specification
Remove the preceeding zero in the constant expression
      that cause the simulator to warn about incorrect
      bit size.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-07-09 10:51:10 +02:00
Michael Cardell Widerkrantz
d297514e7e
doc: Note where doc is to be found
- Not all documentation is in the Dev Handbook.
- Point out README files.
2024-07-01 17:09:29 +02:00
Michael Cardell Widerkrantz
f1534e5dad
doc: Update and expand firmware README
- Remove all text about other software than firmware.
- Remove the Reset section.
- Include a diagram and detailed explanation about the state machine
  in close vicinity.
- Describe the test firmware.

Co-authored-by: Joachim Strömbergson <joachim@assured.se>
2024-07-01 17:09:22 +02:00
Michael Cardell Widerkrantz
cc16c8481c
doc: Move software.md to fw/README 2024-06-27 22:22:14 +02:00
Michael Cardell Widerkrantz
058c8e970c
docs: Remove firmware protocol description
Point to Developer Handbook description.
2024-06-27 09:03:00 +02:00
dehanj
c406b780ba
Docs: remove framing protocol in favor of using the dev-handbook. 2024-06-27 09:02:59 +02:00
dehanj
354aecbed6
USB: move firmware for usb-to-serial MCU (CH552)
Change links to the new ch552_fw directory.
2024-06-25 15:47:22 +02:00
Joachim Strömbergson
c271b48a53
FPGA: Remove redundant clock cycle counter
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-19 15:48:24 +02:00
Joachim Strömbergson
ec77b15eb8
FPGA: Increase SPI speed
- Change SPI clock from 16 CPU cyles/flank to one cycle/flank
- Remove separate flank length wait states in the FSM

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-19 15:48:07 +02:00
Joachim Strömbergson
8ce07683f8
FPGA: SPI-master improvements
- Changed FSM states to localparams
- Added localparam for SPI clock divisor
- Added internal signal for divisor reached
- Improved comments to clarify code
- Fixed some minor textual nits

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-19 11:51:44 +02:00
dehanj
120956b835
CI: Enable linting in CI again. See #182. 2024-06-17 15:37:13 +02:00
Joachim Strömbergson
d502b59062
FPGA: Ignore combinational loops that we want
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-17 15:37:13 +02:00
Joachim Strömbergson
49e81be1e1
FPGA: Ignore lint warnings in cell library
For Verilator >5.019 `-Wno-GENUNNAMED` needs to be added to LINT_FLAGS
to silence warnings from the cell library.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-17 15:37:13 +02:00
Joachim Strömbergson
bb4469ffda
FPGA: Ignore warnings about blocking assignment in clocked processes
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-17 15:37:13 +02:00
Joachim Strömbergson
5d0358dd2f
FPGA: Add labels for generate statements
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-17 15:37:13 +02:00
Joachim Strömbergson
6d9fc7db11
FPGA: Add core local Makefile for linting the PicoRV32
- Add more flags to catch the issues seen when linting the FPGA.
- Store issues in separate file for viewing. Remove with make clean.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-17 15:27:47 +02:00
dehanj
b4c525695a
Remove redundant RAM address and data scrambling
The RAM address and data scrambling API was called twice, once before filling
RAM with random values, and once after. Since moving to a significantly
better PRNG (xorwow) this is now deemed unnecessary. See issue #225.

This changes both FPGA and firmware hashes.
2024-06-13 12:54:47 +02:00
Joachim Strömbergson
92712a11bf
fw: zeroise FW-RAM instead of RAM
Modify the loop to zeroise the FW-RAM instead of the
RAM. RAM is filled with random data at the start of main().

Changes firmware and bitstream digests.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-12 18:11:10 +02:00
Joachim Strömbergson
f61d254fda
Adding testbench and simulation targets for the SPI master. 2024-06-11 15:28:29 +02:00
Joachim Strömbergson
3bc2453287
A construction of a minimal SPI master.
- NOTE: This is an optional feature, not built by default. Not included
  in the tk1 for sale at Tillitis shop.
- This makes it possible to interface the SPI flash onboard TKey.
- To include the SPI master in the build, use `make application_fpga.bin
  YOSYS_FLAG=-DINCLUDE_SPI_MASTER`.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-11 15:28:29 +02:00
Joachim Strömbergson
eade3e11c5
Fill RAM with random data using xorwow.
xorwow provides significantly better random data, compared to previously
used function. Making it harder to predict what data RAM is filled with.
It adds a startup time of approx 80 ms, but can be compensated with
optimising other parts of the startup routine.

This changes both firmware and fpga hashes.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-11 11:15:00 +02:00
Joachim Strömbergson
09df7ae97f
FPGA: Fix linting of tk1 core
Add simultion models of udi_rom and sb_rbga_drv
      to lint-top target.

      Add ignore statements in tb_sb_rgba_drv to silence
      Verilator on parameters and signals not used in
      the sim model.

      Use RGBLEDEN in simulation model

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-10 14:22:59 +02:00
Joachim Strömbergson
cadf8e9849
FPGA: Add sim model of udi_rom
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-07 12:06:40 +02:00
Joachim Strömbergson
0454e023cd
Ignore application_fpga_par.json
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-04-25 11:29:47 +02:00
Joachim Strömbergson
e961f46e79
Update Verilog version to 2005 for linting
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-04-24 08:44:08 +02:00
Joachim Strömbergson
f655196af7
Clarify the functional description of the touch_sense core
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-04-22 16:03:08 +02:00