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70 Commits 27 Branches 14 Tags 32 MiB
6ce374cd97
Commit Graph

40 Commits

Author SHA1 Message Date
Joachim Strömbergson
6ce374cd97 Merge branch 'main' of github.com:tillitis/tillitis-key1 2022-10-12 10:08:16 +02:00
Joachim Strömbergson
82a64f2b2c
Remove DONE state that added one extra final cycle 2022-10-12 10:06:41 +02:00
Daniel Lublin
200ef26f36
Correct 2022-10-11 20:46:21 +02:00
Daniel Lublin
4d927ce426
Fix size_mismatch for testfw 2022-10-11 17:25:19 +02:00
Daniel Lublin
96746b2de0
Clarify BRAM_FW_SIZE 2022-10-11 17:25:00 +02:00
Joachim Strömbergson
24cf80af32
Remove redundant spram module 2022-10-11 13:27:57 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG 2022-10-11 13:17:04 +02:00
Joachim Strömbergson
af36a40f3e Merge branch 'new_trng' 2022-10-11 13:00:13 +02:00
Joachim Strömbergson
5087a67376
Reduce FW ROM size to 6 kByte 2022-10-11 12:54:44 +02:00
Joachim Strömbergson
4b929fedf2 Merge branch 'name_version' 2022-10-11 11:30:47 +02:00
Joachim Strömbergson
87dab3fe6d
Remove name, version addresses for cores 2022-10-11 09:55:56 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores 
timer
       touch_sense
       figaro
       uart
       uds
 2022-10-11 09:50:45 +02:00
Joachim Strömbergson
cdbe71d40d
Add new ROSC based TRNG with VN decorrelation 2022-10-11 08:45:06 +02:00
Joachim Strömbergson
4ed27b4460
Add new rosc based entropy source 2022-10-08 18:37:48 +02:00
Michael Cardell Widerkrantz
df7a26c28c
Compile firmware with -DNOCONSOLE 2022-10-07 11:19:53 +02:00
Joachim Strömbergson
c90771fe19
Remove API access to current prescaler value 2022-10-06 15:56:13 +02:00
Joachim Strömbergson
cc59d8dc93
Update verilator top level module to match rom module changes 2022-10-06 13:59:01 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following: 
Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
 2022-10-06 13:23:30 +02:00
Daniel Lublin
2bb62af183
Update bit divisor calc in verilator's uart to our current 18 MHz 2022-10-03 13:11:53 +02:00
Joachim Strömbergson
6f31bbe37a Merge branch 'main' of github.com:tillitis/tillitis-key1 2022-10-03 12:56:41 +02:00
Joachim Strömbergson
b2ca3f2ea0
Fix Verilator sim by adding separate reset generator 2022-10-03 12:55:24 +02:00
Daniel Lublin
0d16dd5959
Adjust flashing after frequency bump 2022-10-03 08:06:29 +02:00
Daniel Lublin
3f61182a88
Doc how qemu needs to be built; nits 2022-09-30 11:34:09 +02:00
Joachim Strömbergson
1aa2d7bd95 Merge branch 'pll' 2022-09-30 10:06:48 +02:00
Joachim Strömbergson
f41573cc60
Update bit counter to match 18 MHz clock frequency 2022-09-30 10:04:37 +02:00
Joachim Strömbergson
90dc2da8c3
Merge pull request #5 from tillitis/kicad-links 
Fix broken links in kicad library readme
 2022-09-30 08:34:53 +02:00
Daniel Lublin
99efb78ed8
Receive USS and hash into CDI 
- We're OK with USS not being loaded, and use an all-zero USS if so.
- We require USS to be loaded before app_size (if at all).
 2022-09-29 14:58:23 +02:00
Daniel Lublin
df67966d8f
Be consistent and check for errors first 2022-09-28 10:34:48 +02:00
Joachim Strömbergson
f09ff87f9e
Support DIV instructions and catch illegal instructions 2022-09-28 10:29:00 +02:00
Joachim Strömbergson
90a57c4948
Use PLL and global buffer to increas clock speed 2022-09-27 16:41:38 +02:00
Joachim Strömbergson
610522201b
Remove AXI and WB interface modules 2022-09-27 09:48:54 +02:00
Daniel Lublin
10b7951933
Let verilator print when touched by kill -USR1 2022-09-21 11:25:13 +02:00
Daniel Lublin
8066c1092e
Make fmt output changes that will be made 2022-09-21 10:13:39 +02:00
Björn Töpel
2f59eaacdc Add default values to tpt.py 
Provide default values for vendor id, product id, revision number, and
serial number.
 2022-09-21 09:49:07 +02:00
Joachim Strömbergson
43ec0641c0
Change uss to ent to remove confusion 2022-09-21 09:38:44 +02:00
Daniel Lublin
40803993e1
Make synth.json depend on data/{uds,udi}.hex; revise docs 2022-09-20 16:37:04 +02:00
Matthew Mets
dc38b1309a Fix broken links in kicad library readme 2022-09-20 14:08:14 +02:00
Joachim Strömbergson
9d5e1c5ad5
Remove debug output of arguments 2022-09-19 12:37:27 +02:00
Joachim Strömbergson
3110d1218d
Silence lint re missing pins on cell instances 2022-09-19 10:35:49 +02:00
Joachim Strömbergson
715de60f4a Make initial public release 2022-09-19 08:51:11 +02:00