606 Commits

Author SHA1 Message Date
Mikael Ågren
4363637afa
fpga: Trap when executing from ROM in app mode
Only allow executing from ROM when in one of the following execution
contexts:
- Firmware mode
- Syscall

Co-authored-by: Daniel Jobson <jobson@tillitis.se>
2025-02-27 14:20:38 +01:00
Michael Cardell Widerkrantz
5eb020275b
fpga/fw/testfw: Remove Blake2s register
Since the introduction of the syscall mechanism we don't allow
execution in ROM anymore so it's impossible to call the firmware's
blake2s() function.

Co-authored-by: Mikael Ågren <mikael@tillitis.se>
2025-02-27 14:20:38 +01:00
Daniel Jobson
24ef39b739
fpga: Automatically control app_mode in hardware
Instead of manually switching to app mode using the APP_MODE register,
app mode will be enabled when the CPU fetches an instruction outside of
firmware ROM.

Co-authored-by: Mikael Ågren <mikael@tillitis.se>
2025-02-27 14:20:38 +01:00
Mikael Ågren
97de5e68fd
fpga/fw: Rename system_mode to app_mode
Rename `system_mode` to `app_mode` as to not confuse it with syscall or
firmware mode. When `app_mode` is `1`/`true` we are in app mode.
2025-02-27 14:20:37 +01:00
Mikael Ågren
19ae709c81
fpga: Add syscall interrupt
Add syscall interrupt to be used for syscalls. The interrupt is
triggered by writing to an address in the 0xe1000000-0xe1ffffff

The PicoRV32 core is configured to use its minimal, non RISCV-standard,
interrupt implementation.
2025-02-27 14:20:28 +01:00
Mikael Ågren
dd48b77047
tb: Check security monitor read access protection 2025-02-26 13:38:28 +01:00
Mikael Ågren
03c0ca7c86
tb: Display errors in tb_tk1 even if DEBUG is 0
Always display errors to make them easy to find and troubleshoot.
2025-02-26 11:16:23 +01:00
Mikael Ågren
b1047b3618
tb: Write data only once per call to write_word() in tb_tk1
Keep WE and CS high for one clock cycle instead of two. To avoid writing
the same address twice.
2025-02-26 11:16:23 +01:00
Mikael Ågren
0b829cc9ee
.gitignore: compile_commands.json and .cache 2025-02-26 11:16:18 +01:00
Jonas Thörnblad
46ef63ee2d
ch552: Misc. fixes and cleanup
- Move copying of TKEYCTRL data from UartRxBuf to TkeyCtrlRxBuf to align
  with previous code.

- Remove obsolete UartRxBufOverflow variable.

- Add missing Endpoint4 handling for USB bus reset.

- Fix more robust uart_byte_count() calculation.

- Fix baudrate fast mode calculation to get rid of compiler warning.

- Fix assignment of bUD_PD_DIS to UDEV_CTRL.

- Cleanup comments.
2025-02-25 14:40:26 +01:00
Jonas Thörnblad
0b75d25431
ch552: Fix race condition
- Move "EndpointXUploadBusy = 1" to before USB transfer is started to fix
  race with USB transfer complete interrupt.
2025-02-25 14:36:03 +01:00
Jonas Thörnblad
8f2f312531
fpga/fw: Resize ROM and FW_RAM, add RESETINFO partition
In order to be able to leave data for firmware signalling the
intention with a reset or to leave data for the next app in a chain of
apps, we introduce a part of FW_RAM that can be used to store this
data. In order to do this, we:

- Change size of ROM from 6 KB to 8 KB.
- Change size of FW_RAM, from 2 KB to 4 KB.
- Add RESETINFO memory partition inside FW_RAM.
- Add generation of map file.
- Change CFLAGS from using -O2 to using -Os.
- Update address ranges for valid access to ROM and FW_RAM.
- Move stack to be located before data+bss and the RESETINFO data
  above them. This also means we introduce hardware stack overflow
  protection through the Security Monitor.
- Revise firmware README to the new use of FW_RAM.
2025-02-21 11:15:34 +01:00
Michael Cardell Widerkrantz
3126a9c51e
doc: Revise threat model for spelling
- Spell out Chaos Communication Congress.
- Correct spealling of weaknesses.
2025-02-18 09:40:52 +01:00
Michael Cardell Widerkrantz
9a301403e1
doc: Update copyright notice on CH552 fw 2025-02-13 13:49:29 +01:00
Michael Cardell Widerkrantz
de32c58355
doc: Note in CH552 fw where to find CH55x Reset Controller 2025-02-12 14:09:20 +01:00
Michael Cardell Widerkrantz
b7ce031bd6
doc: Revise release notes
- Make it even clearer that legacy device apps WILL NOT WORK.
- Add helpful links to the CH55x Reset Controller, both where to buy
  one and source repo.
2025-02-12 14:09:16 +01:00
Michael Cardell Widerkrantz
d2c7fb0ba9
doc: Update firmware README to include USB Mode Protocol
+ minor link and typo fixes.
2025-02-11 15:21:02 +01:00
Michael Cardell Widerkrantz
179c13e9bf
build: Update digests of firmware and bitstream 2025-02-11 14:40:01 +01:00
Michael Cardell Widerkrantz
050e0f2673
fpga: Format Verilog 2025-02-11 14:37:29 +01:00
Michael Cardell Widerkrantz
aedd6102ea
testfw: Add support for USB Mode Protocol 2025-02-11 14:10:57 +01:00
Michael Cardell Widerkrantz
f68414c4aa
ci: Include Verilog formatting check in CI
- Change checkfmt make target to run both Verilog formatting check and
  C code formatting check.

- Make check formatting it's own job in the CI.
2025-02-11 13:50:08 +01:00
Michael Cardell Widerkrantz
75ad033e03
build: Add -Wno-GENUNNAMED to LINT_FLAGS
For ages we have had a comment saying:

  For Verilator 5.019 -Wno-GENUNNAMED needs to be added to LINT_FLAGS for the
  cell library.

With the new tkey-builder we have 5.028, so it's time to apply this flag.
2025-02-11 13:50:08 +01:00
Michael Cardell Widerkrantz
05bb999759
build/ci: Use new tkey-builder
Use the release candidate for tkey-builder:5
2025-02-11 13:50:07 +01:00
Michael Cardell Widerkrantz
81ac7bffa0
podman/docker: Run bash as login shell
To get bash to source /etc/profile and get the goodness of
/etc/profile/bash_completion.sh, run bash as a login shell.
2025-02-11 13:50:07 +01:00
Michael Cardell Widerkrantz
bb18d5b9e9
toolchain: Introduce buildtools.sh script
Instead of repeated RUNs in Dockerfile, move the entire build of
specific tools to a script.

- Make commands more shell script-like.
- icestorm: Make sure we checkout the right commit.
- Add checks for the right digest for all git clones, so no history
  has been changed.
- Add digest file and check for the downloaded tarball.
tkey-builder-5rc1
2025-02-11 13:50:07 +01:00
Michael Cardell Widerkrantz
8ed16fff6a
docs: Add Castor release notes so far
Breaking change! The introduction of the USB Controller Protocol means
we have a breaking change that makes device apps unable to
communicate.
2025-02-11 13:50:06 +01:00
Jonas Thörnblad
c292595ee3
ch552: Raise UART IRQ priority and tune USB polling period
Set UART1 IRQ to high priority to not miss any incoming bytes
and tune USB polling period (bInterval).
2025-02-11 13:50:06 +01:00
Jonas Thörnblad
361890042a
ch552: Update USB polling period
Update USB polling period (bInterval) for CDC, HID and TKEYCTRL
endpoints.
2025-02-11 13:50:06 +01:00
Jonas Thörnblad
5029eb1d39
ch552: Fix CDC configuration problem on Windows
Fix CDC configuration problem on Windows when we have a composite
device (multiple different Device Classes). Add "Interface Association
Descriptor" to make it work.
2025-02-11 13:50:05 +01:00
Jonas Thörnblad
04ec938200
ch552: Add new USB debug pipe (TKEYCTRL)
Make the CH552 present a new HID endpoint used for debug data.
2025-02-11 13:50:05 +01:00
Jonas Thörnblad
bfc43093ec
fpga: Fix bitrate counter bug
Fix off-by-one UART bitrate counter value that will make the RX
sampling and TX sending drift. The impact gets higher as the baudrate
increases and the bitrate counter value gets smaller.
2025-02-11 13:50:05 +01:00
Jonas Thörnblad
07dc20e4e1
fpga/testfw: Update clock frequency to 24 MHz
Reconfigure the baudrate to keep 500 kbaud.

Correct a forgotten test in testfw that wasn't updated the last time
frequency was raised in commit
75b028505f0d6dc685d37b84d73ddb9db5ee7ea2 in June 17, 2024.
2025-02-11 13:50:04 +01:00
Jonas Thörnblad
0a634c76da
ch552: Use the new hardware CTS signals for UART access
- Use CTS signals to let the FPGA and CH552 signal each other that
    it is OK send UART data.
  - Update the CH552 rx and frame handling logic.
  - Fix minor spelling errors and indentation
2025-02-11 13:50:04 +01:00
Jonas Thörnblad
ab4ef5fdf9
fpga: Introduce CTS signals for UART
Add incoming and outgoing CTS (Clear To Send) signals for the FPGA to
let the CH552 and FPGA signal each other that it is OK to send UART
data. The CTS signals indicate "OK to send" if high. If an incoming
CTS signal goes low, the receiver of that signal should immediatly
stop sending UART data.
2025-02-11 13:50:04 +01:00
Mikael Ågren
f3706dcfcc
fpga: Increase UART baud rate to 500k 2025-02-11 13:50:03 +01:00
Mikael Ågren
a0c031eb25
fw: Minimal CDC implementation of new framing protocol
Throwing away mode and length from incoming data. Adding mode and
length to outgoing data.

Splitting responses into frames small enough for the USB<->UART
transceiver to handle.
2025-02-11 13:50:03 +01:00
Mikael Ågren
1b9bbc4eba
ch552: Wrap accesses to UART output buffers 2025-02-06 16:20:34 +01:00
Jonas Thörnblad
b443359e9c
ch552: Add USB HID and protocol support over UART
- Add USB HID support.
- Introduce a small protocol to distinguish between CDC and HID data
  sent over the UART.
- Add some debug printing.
- Cleanup of code and formatting.
2025-02-06 16:20:34 +01:00
Jonas Thörnblad
90fca5d3dd
ch552: Move usb_strings.h to the include directory 2025-02-06 16:20:34 +01:00
Jonas Thörnblad
0af82ee566
fpga/fw: Extend checks for invalid memory accesses
- Extend hardware checks for invalid memory accesses to include
  checking more address space.

- In fw include file: fix two typos for memory ranges that relates to
  above that fortunately have no impact on functionality.
2025-02-06 16:16:46 +01:00
Michael Cardell Widerkrantz
a5ed3cfaa9
Build: Don't depend on uds.hex and udi.hex
synth.json shouldn't depend on uds.hex and udi.hex because that
triggers a complete rebuild of the bitstream if the UDI or UDS are
changed.

Instead, we want only the application_fpga.asc to depend on them, so
we can patch in the UDS and UDI with tools/patch_uds_udi.py in an
existing application_fpga_par.json.
2025-01-20 14:48:53 +01:00
Daniel Jobson
66888a3756
tb: Make uart selftesting
- Exit with the right exit code
2024-12-09 13:55:43 +01:00
Daniel Jobson
c637c745cc
tb: Make trng selftesting
- Exit with the right error code
2024-12-09 13:55:43 +01:00
Daniel Jobson
ac853c87ec
tb: Make touch_sense selftesting
- Check for expected word
- Exit with the right error code
2024-12-09 13:55:42 +01:00
Daniel Jobson
c547042553
tb: Make tb_tk1_spi_master.v selftesting
- Compare against expected value
- Exit with the correct error code
2024-12-09 13:55:42 +01:00
Daniel Jobson
09c3d9b58e
tb: Make tb_tk1.v selftesting
- Exit with the right error code
2024-12-09 09:42:42 +01:00
Jonas Thörnblad
07dec8b8dc
Add make target for testbench simulation and simulation firmware.
Create separate sources for FPGA specific code, testbench simulation
specific code, verilator simulation specific code.
2024-11-28 16:10:01 +01:00
Jonas Thörnblad
ede92af2c1
Updated application_fpga_verilator.cc to match module application_fpga_sim.
- include printout of used clock and baud rate speed
- Use the the same clock frequency as target
2024-11-28 16:10:01 +01:00
Jonas Thörnblad
48c9709164
Set APP_SIZE if not defined. 2024-11-28 16:10:01 +01:00
Jonas Thörnblad
a99e69f33e
Remove non-working make targets for "post-synthesis functional simulation"
and "post-place and route functional simulation".
2024-11-28 16:10:00 +01:00