mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-12-24 06:59:24 -05:00
Add make target for testbench simulation and simulation firmware.
Create separate sources for FPGA specific code, testbench simulation specific code, verilator simulation specific code.
This commit is contained in:
Jonas Thörnblad
Daniel Jobson
parent
ede92af2c1
commit
07dec8b8dc
4
.gitignore
vendored
4
.gitignore
vendored
@ -33,6 +33,10 @@ synth.txt
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synth.v
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application_fpga_par.json
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application_fpga_par.txt
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tb_application_fpga_sim.fst
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tb_application_fpga_sim.fst.hier
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tb_verilated/
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verilated/
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*.o
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*.asc
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*.bin
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@ -73,14 +73,23 @@ ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v)
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# FPGA specific source files.
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FPGA_SRC = \
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FPGA_VERILOG_SRCS = \
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$(P)/rtl/application_fpga.v \
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$(P)/core/clk_reset_gen/rtl/clk_reset_gen.v
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$(P)/core/clk_reset_gen/rtl/clk_reset_gen.v \
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$(P)/core/trng/rtl/trng.v
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# Testbench simulation specific source files.
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SIM_VERILOG_SRCS = \
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$(P)/tb/tb_application_fpga_sim.v \
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$(P)/tb/application_fpga_sim.v \
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$(P)/tb/reset_gen_sim.v \
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$(P)/tb/trng_sim.v
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# Verilator simulation specific source files.
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VERILATOR_FPGA_SRC = \
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VERILATOR_VERILOG_SRCS = \
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$(P)/tb/application_fpga_sim.v \
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$(P)/tb/reset_gen_sim.v
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$(P)/tb/reset_gen_sim.v \
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$(P)/tb/trng_sim.v
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# Common verilog source files.
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VERILOG_SRCS = \
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@ -97,8 +106,7 @@ VERILOG_SRCS = \
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$(P)/core/tk1/rtl/udi_rom.v \
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$(P)/core/uart/rtl/uart_core.v \
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$(P)/core/uart/rtl/uart_fifo.v \
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$(P)/core/uart/rtl/uart.v \
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$(P)/core/trng/rtl/trng.v
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$(P)/core/uart/rtl/uart.v
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# PicoRV32 verilog source file
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PICORV32_SRCS = \
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@ -176,6 +184,10 @@ $(TESTFW_OBJS): $(FIRMWARE_DEPS)
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firmware.elf: $(FIRMWARE_OBJS) $(P)/fw/tk1/firmware.lds
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$(CC) $(CFLAGS) $(FIRMWARE_OBJS) $(LDFLAGS) -o $@
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simfirmware.elf: CFLAGS += -DSIMULATION
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simfirmware.elf: $(FIRMWARE_OBJS) $(P)/fw/tk1/firmware.lds
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$(CC) $(CFLAGS) $(FIRMWARE_OBJS) $(LDFLAGS) -o $@
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qemu_firmware.elf: CFLAGS += -DQEMU_CONSOLE
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qemu_firmware.elf: firmware.elf
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mv firmware.elf qemu_firmware.elf
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@ -216,6 +228,8 @@ bram_fw.hex:
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firmware.hex: firmware.bin firmware_size_mismatch
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python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
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simfirmware.hex: simfirmware.bin simfirmware_size_mismatch
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python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
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testfw.hex: testfw.bin testfw_size_mismatch
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python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
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@ -249,7 +263,11 @@ LINT_FLAGS = \
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--timescale 1ns/1ns \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS
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lint: $(FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) $(ICE40_SIM_CELLS)
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lint: $(FPGA_VERILOG_SRCS) \
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$(SIM_VERILOG_SRCS) \
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$(VERILOG_SRCS) \
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$(PICORV32_SRCS) \
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$(ICE40_SIM_CELLS)
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$(LINT) $(LINT_FLAGS) \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
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@ -278,13 +296,13 @@ CHECK_FORMAT_FLAGS = \
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--inplace \
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--verify
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fmt: $(FPGA_SRC) $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS)
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fmt: $(FPGA_VERILOG_SRCS) $(SIM_VERILOG_SRCS) $(VERILATOR_VERILOG_SRCS) $(VERILOG_SRCS)
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$(FORMAT) $(FORMAT_FLAGS) $^
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.PHONY: fmt
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# Temporary fix using grep, since the verible with --verify flag only returns
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# error if the last file is malformatted.
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checkfmt: $(FPGA_SRC) $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS)
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checkfmt: $(FPGA_VERILOG_SRCS) $(SIM_VERILOG_SRCS) $(VERILATOR_VERILOG_SRCS) $(VERILOG_SRCS)
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$(FORMAT) $(CHECK_FORMAT_FLAGS) $^ 2>&1 | \
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grep "Needs formatting" && exit 1 || true
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.PHONY: checkfmt
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@ -292,7 +310,7 @@ checkfmt: $(FPGA_SRC) $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS)
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#-------------------------------------------------------------------
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# Build Verilator compiled simulation for the design.
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#-------------------------------------------------------------------
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verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) \
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verilator: $(VERILATOR_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) \
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firmware.hex $(ICE40_SIM_CELLS) \
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$(P)/tb/application_fpga_verilator.cc
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verilator \
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@ -301,6 +319,7 @@ verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) \
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-Wall \
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-Wno-COMBDLY \
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-Wno-lint \
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-Wno-UNOPTFLAT \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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@ -308,10 +327,10 @@ verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) \
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--cc \
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--exe \
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--Mdir verilated \
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--top-module application_fpga \
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--top-module application_fpga_sim \
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$(filter %.v, $^) \
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$(filter %.cc, $^)
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make -C verilated -f Vapplication_fpga.mk
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make -C verilated -f Vapplication_fpga_sim.mk
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.PHONY: verilator
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#-------------------------------------------------------------------
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@ -334,7 +353,7 @@ tb:
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YOSYS_FLAG ?=
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synth.json: $(FPGA_SRC) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex \
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synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex \
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$(P)/data/uds.hex $(P)/data/udi.hex
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$(YOSYS_PATH)yosys \
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-v3 \
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@ -380,6 +399,44 @@ application_fpga_testfw.bin: application_fpga.asc bram_fw.hex testfw.hex
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$(ICESTORM_PATH)icepack $<.tmp $@
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@-$(RM) $<.tmp
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#-------------------------------------------------------------------
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# Build testbench simulation for the design
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#-------------------------------------------------------------------
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tb_application_fpga: $(SIM_VERILOG_SRCS) \
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$(VERILOG_SRCS) \
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$(PICORV32_SRCS) \
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$(ICE40_SIM_CELLS) \
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simfirmware.hex
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python3 ./tools/app_bin_to_spram_hex.py \
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./tb/app.bin \
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./tb/output_spram0.hex \
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./tb/output_spram1.hex \
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./tb/output_spram2.hex \
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./tb/output_spram3.hex \
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|| { echo -e "\n -- Put your app.bin to simulate in the \"tb\" directory\n"; false; }
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verilator \
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-j $(shell nproc --ignore=1) \
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--binary \
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--cc \
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--exe \
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--Mdir tb_verilated \
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--trace-fst \
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--trace-structs \
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--top-module tb_application_fpga_sim \
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--timescale 1ns/1ns \
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--timing \
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-Wno-WIDTHEXPAND \
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-Wno-UNOPTFLAT \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS \
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-DAPP_SIZE=$(shell ls -l tb/app.bin| awk '{print $$5}') \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/simfirmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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$(filter %.v, $^)
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make -C tb_verilated -f Vtb_application_fpga_sim.mk
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./tb_verilated/Vtb_application_fpga_sim \
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&& { echo -e "\n -- Wave simulation saved to tb_application_fpga_sim.fst\n"; true; }
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#-------------------------------------------------------------------
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# FPGA device programming.
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@ -413,12 +470,11 @@ view: tb_application_fpga_vcd
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#-------------------------------------------------------------------
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# Cleanup.
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#-------------------------------------------------------------------
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clean: clean_fw clean_tb
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clean: clean_sim clean_fw clean_tb
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rm -f bram_fw.hex
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rm -f synth.{v,json,txt} application_fpga.{asc,bin} application_fpga_testfw.bin
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rm -f application_fpga_par.{json,txt}
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rm -f lint_issues.txt
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rm -rf verilated
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rm -f tools/tpt/*.hex
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rm -rf tools/tpt/__pycache__
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.PHONY: clean
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@ -431,6 +487,15 @@ clean_fw:
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rm -f qemu_firmware.elf
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.PHONY: clean_fw
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clean_sim:
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rm -f simfirmware.{elf,elf.map,bin,hex}
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rm -f tb_application_fpga_sim.fst
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rm -f tb_application_fpga_sim.fst.hier
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rm -f tb/output_spram*.hex
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rm -rf tb_verilated
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rm -rf verilated
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.PHONY: clean_sim
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clean_tb:
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make -C core/timer/toolruns clean
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make -C core/tk1/toolruns clean
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@ -449,20 +514,21 @@ help:
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@echo ""
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@echo "Supported targets:"
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@echo "------------------"
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@echo "all Build all targets."
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@echo "check Run static analysis on firmware."
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@echo "splint Run splint static analysis on firmware."
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@echo "firmware.elf Build firmware ELF file."
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@echo "firmware.hex Build firmware converted to hex, to be included in bitstream."
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@echo "bram_fw.hex Build a fake BRAM file that will be filled in later after place-n-route."
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@echo "verilator Build Verilator simulation program"
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@echo "lint Run lint on Verilog source files."
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@echo "tb Run all testbenches"
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@echo "prog_flash Program device flash with FGPA bitstream including firmware (using the RPi Pico-based programmer)."
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@echo "prog_flash_testfw Program device flash as above, but with testfw."
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@echo "clean Delete all generated files."
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@echo "clean_fw Delete only generated files for firmware. Useful for fw devs."
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@echo "clean_tb Delete only generated files for testbenches."
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@echo "all Build all targets."
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@echo "check Run static analysis on firmware."
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@echo "splint Run splint static analysis on firmware."
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@echo "firmware.elf Build firmware ELF file."
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@echo "firmware.hex Build firmware converted to hex, to be included in bitstream."
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@echo "bram_fw.hex Build a fake BRAM file that will be filled in later after place-n-route."
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@echo "verilator Build Verilator simulation program"
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@echo "tb_application_fpga Build testbench simulation for the design"
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@echo "lint Run lint on Verilog source files."
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@echo "tb Run all testbenches"
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@echo "prog_flash Program device flash with FGPA bitstream including firmware (using the RPi Pico-based programmer)."
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@echo "prog_flash_testfw Program device flash as above, but with testfw."
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@echo "clean Delete all generated files."
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@echo "clean_fw Delete only generated files for firmware. Useful for fw devs."
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@echo "clean_tb Delete only generated files for testbenches."
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#=======================================================================
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# EOF Makefile
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