fpga/testfw: Update clock frequency to 24 MHz

Reconfigure the baudrate to keep 500 kbaud.

Correct a forgotten test in testfw that wasn't updated the last time
frequency was raised in commit
75b028505f0d6dc685d37b84d73ddb9db5ee7ea2 in June 17, 2024.

hw/application_fpga/Makefile

@@ -28,7 +28,7 @@ ICESTORM_PATH ?=
 
 # FPGA target frequency. Should be in sync with the clock frequency
 # given by the parameters to the PLL in rtl/clk_reset_gen.v
-TARGET_FREQ ?= 21
+TARGET_FREQ ?= 24
 
 # Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
 # bits wide; an EBR is 128 32-bits words)
@@ -367,6 +367,7 @@ synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex
 application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
 	$(NEXTPNR_PATH)nextpnr-ice40 \
 		-l application_fpga_par.txt \
+		--seed 4384471485005169719 \
 		--freq $(TARGET_FREQ) \
 		--ignore-loops \
 		--up5k \

hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v

@@ -76,13 +76,13 @@ module clk_reset_gen #(
   //
   // F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
   //
-  // Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
+  // Given the 12 MHz HFOSC clock set above, we get a final 24 MHz:
   //
-  // (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
+  // (12000000 * (63 + 1)) / (2^5 * (0 + 1)) = 24000000
   SB_PLL40_CORE #(
       .FEEDBACK_PATH("SIMPLE"),
       .DIVR(4'd0),  // DIVR =  0
-      .DIVF(7'd55),  // DIVF = 55
+      .DIVF(7'd63),  // DIVF = 63
       .DIVQ(3'd5),  // DIVQ =  5
       .FILTER_RANGE(3'b001)  // FILTER_RANGE = 1
   ) pll_inst (

hw/application_fpga/core/uart/rtl/uart.v

@@ -82,10 +82,10 @@ module uart (
   // The default bit rate is based on target clock frequency
   // divided by the bit rate times in order to hit the
   // center of the bits. I.e.
-  // Clock: 21 MHz, 500 kbps
-  // Divisor = 21E6 / 500E3 = 42
+  // Clock: 24 MHz, 500 kbps
+  // Divisor = 24E6 / 500E3 = 48
   // This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
-  localparam DEFAULT_BIT_RATE  = 16'd42;
+  localparam DEFAULT_BIT_RATE = 16'd48;
   localparam DEFAULT_DATA_BITS = 4'h8;
   localparam DEFAULT_STOP_BITS = 2'h1;
 

hw/application_fpga/fw/testfw/main.c

@@ -311,8 +311,8 @@ int main(void)
 	}
 
 	puts("\r\nTesting timer... 3");
-	// Matching clock at 18 MHz, giving us timer in seconds
-	*timer_prescaler = 18 * 1000000;
+	// Matching clock at 24 MHz, giving us timer in seconds
+	*timer_prescaler = 24 * 1000000;
 
 	// Test timer expiration after 1s
 	*timer = 1;