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https://github.com/tillitis/tillitis-key1.git
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Remove non-working make targets for "post-synthesis functional simulation"
and "post-place and route functional simulation".
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@ -380,42 +380,6 @@ application_fpga_testfw.bin: application_fpga.asc bram_fw.hex testfw.hex
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$(ICESTORM_PATH)icepack $<.tmp $@
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@-$(RM) $<.tmp
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#-------------------------------------------------------------------
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# post-synthesis functional simulation.
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#-------------------------------------------------------------------
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synth_tb.vvp: $(P)/tb/tb_application_fpga.v synth.json
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iverilog \
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-o $@ \
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-s tb_application_fpga synth.v $(P)/tb/tb_application_fpga.v \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS \
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$(ICE40_SIM_CELLS)
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chmod -x $@
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synth_sim: synth_tb.vvp
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vvp -N $<
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.PHONY: synth_sim
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synth_sim_vcd: synth_tb.vvp
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vvp -N $< +vcd
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.PHONY: synth_sim_vcd
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#-------------------------------------------------------------------
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# post-place and route functional simulation.
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#-------------------------------------------------------------------
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route.v: application_fpga.asc $(P)/data/$(PIN_FILE)
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icebox_vlog -L -n application_fpga -sp $(P)/data/$(PIN_FILE) $< > $@
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route_tb.vvp: route.v tb/tb_application_fpga.v
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iverilog -o $@ -s tb_application_fpga $^ $(ICE40_SIM_CELLS)
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chmod -x $@
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route_sim: route_tb.vvp
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vvp -N $<
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.PHONY: route_sim
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route_sim_vcd: route_tb.vvp
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vvp -N $< +vcd
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.PHONY: route_sim_vcd
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#-------------------------------------------------------------------
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# FPGA device programming.
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@ -451,10 +415,8 @@ view: tb_application_fpga_vcd
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#-------------------------------------------------------------------
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clean: clean_fw clean_tb
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rm -f bram_fw.hex
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rm -f synth.{v,json,txt} route.v application_fpga.{asc,bin,vcd} application_fpga_testfw.bin
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rm -f tb_application_fpga.vvp synth_tb.vvp route_tb.vvp
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rm -f synth.{v,json,txt} application_fpga.{asc,bin} application_fpga_testfw.bin
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rm -f application_fpga_par.{json,txt}
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rm -f *.vcd
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rm -f lint_issues.txt
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rm -rf verilated
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rm -f tools/tpt/*.hex
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