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fpga: Format Verilog

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This commit is contained in:
Michael Cardell Widerkrantz 2025-02-11 14:37:29 +01:00
parent aedd6102ea
commit 050e0f2673
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GPG Key ID: D3DB3DDF57E704E5
4 changed files with 6 additions and 6 deletions
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2
hw/application_fpga/core/uart/rtl/uart_core.v
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@ -360,7 +360,7 @@ module uart_core (
// Just a glitch.
rxd_bitrate_ctr_rst = 1;
erx_ctrl_new = ERX_IDLE;
erx_ctrl_we = 1;
erx_ctrl_we = 1;
end
else begin

2
hw/application_fpga/core/uart/rtl/uart_fifo.v
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@ -50,7 +50,7 @@ module uart_fifo (
output wire [7 : 0] out_data,
input wire out_ack,
output wire fpga_cts
output wire fpga_cts
);

6
hw/application_fpga/rtl/application_fpga.v
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@ -20,8 +20,8 @@ module application_fpga (
output wire interface_rx,
input wire interface_tx,
input wire interface_ch552_cts, // CH552 clear to send, 1 = OK, 0 = NOK
output wire interface_fpga_cts, // FPGA clear to send, 1 = OK, 0 = NOK
input wire interface_ch552_cts, // CH552 clear to send, 1 = OK, 0 = NOK
output wire interface_fpga_cts, // FPGA clear to send, 1 = OK, 0 = NOK
output wire spi_ss,
output wire spi_sck,
@ -297,7 +297,7 @@ module application_fpga (
.txd(interface_rx),
.ch552_cts(interface_ch552_cts),
.fpga_cts(interface_fpga_cts),
.fpga_cts (interface_fpga_cts),
.cs(uart_cs),
.we(uart_we),

2
hw/application_fpga/tb/application_fpga_sim.v
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@ -308,7 +308,7 @@ module application_fpga_sim (
.txd(interface_rx),
.ch552_cts(interface_ch552_cts),
.fpga_cts(interface_fpga_cts),
.fpga_cts (interface_fpga_cts),
.cs(uart_cs),
.we(uart_we),