Daniel Lublin
ff1bf1f326
Merge pull request #32 from tillitis/clear-ram
...
FW: Clear all RAM during start
2022-10-24 11:56:16 +02:00
Michael Cardell Widerkrantz
490571b6c0
Clear all RAM during start
...
Since SRAM has some data remanence even without power it seems good
hygien to clear all RAM when starting the device so as not to leak
potential sensitive data between device apps.
2022-10-24 11:52:52 +02:00
Daniel Lublin
1661ac20d4
tpt: correct and clarify ranges
2022-10-24 10:05:05 +02:00
Daniel Lublin
ecc2923387
Explain how we attain 18 MHz
2022-10-21 14:33:03 +02:00
Daniel Lublin
675fa1087f
Raise bps to 62500
2022-10-21 14:10:41 +02:00
Michael Cardell Widerkrantz
b8f1d4a083
Add make target secret, update quickstart
2022-10-20 17:02:56 +02:00
Daniel Lublin
65f2272a45
Add TRNG to testfw, document
2022-10-20 12:05:19 +02:00
Michael Cardell Widerkrantz
c52f7d52cd
testfw: Add timer tests
2022-10-20 11:34:01 +02:00
Joachim Strömbergson
2531832683
Fix spelling and clarify programming board FW update procedure
2022-10-19 15:59:42 +02:00
Joachim Strömbergson
32312ead28
Fix spellinh nits
2022-10-19 15:27:51 +02:00
Joachim Strömbergson
19b75e71fe
Fix bit counter and simplify emtropy extraction
2022-10-19 13:10:26 +02:00
Joachim Strömbergson
20647fc486
Merge branch 'main' of github.com:tillitis/tillitis-key1
2022-10-19 09:39:23 +02:00
Joachim Strömbergson
c07c15a8b8
Update README to describe the new ROSC based TRNG
2022-10-19 09:37:58 +02:00
Michael Cardell Widerkrantz
cbe6d3db8d
Use the new firmware-only RAM for CDI computation
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To protect UDS we use a special firmware-only RAM for both the in
parameter to the blake2s() function and for the blake2s_ctx.
2022-10-18 14:51:30 +02:00
Michael Cardell Widerkrantz
6d08a82c05
Pass the blake2s_ctx to blake2s() as arg
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Instead of allocating the blake2s_ctx in the blake2s() function we
pass it as a pointer as an argument to be able to better control where
the variable is in memory.
2022-10-18 14:51:26 +02:00
Joachim Strömbergson
e0d68f3dae
Merge branch 'main' of github.com:tillitis/tillitis-key1
2022-10-18 11:31:42 +02:00
Joachim Strömbergson
ddd969870e
Count from init values to one, not zero
2022-10-18 11:06:40 +02:00
Daniel Lublin
7129205cb0
Add fw_ram size to mem-include
2022-10-17 11:38:04 +02:00
Daniel Lublin
69c3f77e5e
testfw: tidy, clean-up, fmt
2022-10-17 11:15:26 +02:00
Joachim Strömbergson
f6046d55a9
Change ADDR_CTRL to be a pulsed start_stop signal
2022-10-14 08:50:30 +02:00
Joachim Strömbergson
c3f7c5fb06
Ignore the prescaler if prescaler init value is zero
2022-10-13 16:24:03 +02:00
Joachim Strömbergson
2be934ee22
Restore start and stop bits, but clarify in documenation
2022-10-13 16:10:08 +02:00
Joachim Strömbergson
50fbc8adc4
Update software description with timer API changes
2022-10-13 15:22:52 +02:00
Joachim Strömbergson
00d180d34e
Change to a single run bit and update access control
2022-10-13 14:58:39 +02:00
Joachim Strömbergson
5e5550461f
Removing confusing negation in message
2022-10-13 13:56:12 +02:00
Joachim Strömbergson
1b03459ab3
Remove app-accessible debug register from mta1 core
2022-10-13 13:51:19 +02:00
Joachim Strömbergson
51a22dc32c
Merge branch 'fw_ram'
2022-10-13 13:16:53 +02:00
Joachim Strömbergson
1f2a585aba
Add test case for fw_ram
2022-10-13 13:16:11 +02:00
Joachim Strömbergson
8e493b6322
Debug fw_ram and add fw_app_mode access control
2022-10-13 13:14:10 +02:00
Joachim Strömbergson
b37b377a7e
Change optimization to Os since we want compact code
2022-10-13 09:26:49 +02:00
Michael Cardell Widerkrantz
99aabe89e9
Fix minor doc nits
2022-10-12 15:12:07 +02:00
Daniel Lublin
55c5081486
Adjust and document the firmware state-machine, including USS
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In particular, order of LOAD_USS and LOAD_APP_SIZE is not required, but
the need to send both is documented. This is followed up with adjustment
in the host programs' Go code, to try to reinforce this. LoadApp() will
take the secretPhrase parameter (to be hashed as USS), and loadUSS()
will be unexported.
Correct CMD/RSP lengths in pseudo-code.
2022-10-12 15:12:07 +02:00
Joachim Strömbergson
5013338e50
Change to a more descriptive name
2022-10-12 11:14:46 +02:00
Joachim Strömbergson
192ce47fce
Fix #18 with incorrect clock frequency in analysis
2022-10-12 10:25:37 +02:00
Joachim Strömbergson
a9fd26da3b
Fix bit bit width mismatches
2022-10-12 10:21:50 +02:00
Joachim Strömbergson
f75860c2a2
Add link to SW page to the list of documents
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The page is linked from the system description page,
but is probably hard to find.
2022-10-12 10:14:07 +02:00
Joachim Strömbergson
c25fc0e7f2
Fix language nits
2022-10-12 10:10:48 +02:00
Joachim Strömbergson
6ce374cd97
Merge branch 'main' of github.com:tillitis/tillitis-key1
2022-10-12 10:08:16 +02:00
Joachim Strömbergson
82a64f2b2c
Remove DONE state that added one extra final cycle
2022-10-12 10:06:41 +02:00
Daniel Lublin
200ef26f36
Correct
2022-10-11 20:46:21 +02:00
Daniel Lublin
4d927ce426
Fix size_mismatch for testfw
2022-10-11 17:25:19 +02:00
Daniel Lublin
96746b2de0
Clarify BRAM_FW_SIZE
2022-10-11 17:25:00 +02:00
Joachim Strömbergson
cbf1104fed
Write whole byte, not nybbles
2022-10-11 17:05:21 +02:00
Joachim Strömbergson
a51619e5b7
Add fw_ram module
2022-10-11 16:58:26 +02:00
Joachim Strömbergson
24cf80af32
Remove redundant spram module
2022-10-11 13:27:57 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG
2022-10-11 13:17:04 +02:00
Joachim Strömbergson
af36a40f3e
Merge branch 'new_trng'
2022-10-11 13:00:13 +02:00
Joachim Strömbergson
5087a67376
Reduce FW ROM size to 6 kByte
2022-10-11 12:54:44 +02:00
Joachim Strömbergson
4b929fedf2
Merge branch 'name_version'
2022-10-11 11:30:47 +02:00
Joachim Strömbergson
1439e4a587
Remove name, version info about cores from SW description
2022-10-11 11:28:40 +02:00
