572 Commits

Author SHA1 Message Date
Jonas Thörnblad
8eade9933c
Add incoming and outgoing CTS (Clear To Send) signals for the CH552
- Add CTS signals let the FPGA and CH552 signal each other that
    it is OK send UART data.
  - Update the CH552 rx and frame handling logic.
  - Fix minor spelling errors and indentation
2024-12-18 11:30:25 +01:00
Jonas Thörnblad
48cbb55d6e
Add incoming and outgoing CTS (Clear To Send) signals for the FPGA
to let the CH552 and FPGA signal each other that it is OK to send
UART data. The CTS signals indicate "OK to send" if high. If an
incoming CTS signal goes low, the receiver of that signal should
immediatly stop sending UART data.
2024-12-17 17:18:45 +01:00
Mikael Ågren
5d138ef45b
FPGA: Increase UART baud rate to 500k 2024-12-16 12:30:50 +01:00
Mikael Ågren
d2a9100412
fw: Minimal CDC implementation of new framing protocol
Throwing away mode and length from incoming data. Adding mode and
length to outgoing data.

Splitting responses into frames small enough for the USB<->UART
transceiver to handle.
2024-12-16 12:25:31 +01:00
Mikael Ågren
8c7059155f
Wrap accesses to UART output buffers 2024-12-16 12:18:43 +01:00
Jonas Thörnblad
a0910e25c3
WIP: Add USB HID and framing support over UART
- Add USB HID support.
- Add framing to distinguish between CDC and HID data sent over the UART.
- Add some debug printing.
- Cleanup of code and formatting.
2024-12-16 12:18:43 +01:00
Jonas Thörnblad
f6c0501db9
Move usb_strings.h for ch552_fw to the include directory 2024-12-16 12:18:43 +01:00
Daniel Jobson
66888a3756
tb: Make uart selftesting
- Exit with the right exit code
2024-12-09 13:55:43 +01:00
Daniel Jobson
c637c745cc
tb: Make trng selftesting
- Exit with the right error code
2024-12-09 13:55:43 +01:00
Daniel Jobson
ac853c87ec
tb: Make touch_sense selftesting
- Check for expected word
- Exit with the right error code
2024-12-09 13:55:42 +01:00
Daniel Jobson
c547042553
tb: Make tb_tk1_spi_master.v selftesting
- Compare against expected value
- Exit with the correct error code
2024-12-09 13:55:42 +01:00
Daniel Jobson
09c3d9b58e
tb: Make tb_tk1.v selftesting
- Exit with the right error code
2024-12-09 09:42:42 +01:00
Jonas Thörnblad
07dec8b8dc
Add make target for testbench simulation and simulation firmware.
Create separate sources for FPGA specific code, testbench simulation
specific code, verilator simulation specific code.
2024-11-28 16:10:01 +01:00
Jonas Thörnblad
ede92af2c1
Updated application_fpga_verilator.cc to match module application_fpga_sim.
- include printout of used clock and baud rate speed
- Use the the same clock frequency as target
2024-11-28 16:10:01 +01:00
Jonas Thörnblad
48c9709164
Set APP_SIZE if not defined. 2024-11-28 16:10:01 +01:00
Jonas Thörnblad
a99e69f33e
Remove non-working make targets for "post-synthesis functional simulation"
and "post-place and route functional simulation".
2024-11-28 16:10:00 +01:00
Jonas Thörnblad
15ce2c438b
Add needed changes to firmware for simulation. 2024-11-28 16:10:00 +01:00
Jonas Thörnblad
fe9055ea23
Add script to split app into simulation ram
Co-authored-by: Mikael Ågren <mikael@tillitis.se>
2024-11-28 16:10:00 +01:00
Jonas Thörnblad
3cd902f792
Add top level testbench for application_fpga_sim.v 2024-11-28 16:10:00 +01:00
Jonas Thörnblad
4260e1d5ac
Update application_fpga_sim.v to match application_fpga.v 2024-11-28 16:10:00 +01:00
Jonas Thörnblad
a330aa15ec
Add verilog file for TRNG simulation 2024-11-28 16:10:00 +01:00
Jonas Thörnblad
d3b9660180
Align module name with its file name. 2024-11-28 16:09:59 +01:00
Jonas Thörnblad
e54045a4dd
Add APP_SIZE parameter to tk1 block to set size of application when simulating. 2024-11-28 16:09:59 +01:00
Daniel Jobson
5b49d80891
tb: make timer core testbench selftesting
- Compare against an expected result and count errors
- Exit with the right error code
- Clean up the output
2024-11-27 08:10:15 +01:00
Daniel Jobson
c735c6fdde
tb: make tb_timer.v selftesting
- Compare against an expected result and count errors
- Exit with the right error code
- Lower write_word() to 1 clk cycle instead of two. It only requires one
  clock cycle to write, otherwise if it is two one have to compensate for it
  in the tests since we are counting cycles.
2024-11-27 08:10:15 +01:00
Daniel Jobson
6bdedf4f86
Fix bug in timer core, where it misses clock cycles
Remove redundant timer state. This fixes a bug where the timer misses a
clock cycle every time the prescaler counter reaches 1. This means if
one uses a large prescaler, like 18E6, it is barely noticeable, but if
one have a low prescaler and a high timer value it becomes significant.
This also yields the running_* registers redundant, which are removed.

Add clarity to the readme.

Update the timer to default to values of one, for prescaler and timer
count.
2024-11-27 08:10:15 +01:00
Daniel Jobson
3d7a97ecbc
fpga: remove the API for configuring the UART core
This removes the possibility to configure the bit rate, data bits and
stop bits at runtime from the API. This reduces the
usage of LCs with ~4%.

It is still possible to configure the core before building.

Update digest of application_fpga.bin.sha256
2024-11-26 15:24:12 +01:00
Jonas Thörnblad
0445c8f993
Add nextpnr flag '--exit-on-failed-target-frequency' 2024-11-22 15:47:42 +01:00
Jonas Thörnblad
08a204dfa6
Minimize number of Dockerfile RUN commands to lower number of
used layers in the image. Too many layers will give an error.
2024-11-22 15:47:41 +01:00
Daniel Jobson
1941a22007
Doc: move implementation details of RAM scrambling to RAM core 2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
de8fcb8768
Remove DCO document 2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
ebd6b17966
Revise top-level README
- Simplify.
- Update links.
- Remove DCO link
2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
86aedcce69
Revise top-level README for the hardware design
Merged information from fpga.md, and hence fpga.md is removed.
2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
9f975bb66f
Add clangd target
Create a compile_commands.json to help clangd for LSP.
2024-11-15 15:01:31 +01:00
Michael Cardell Widerkrantz
fe8f0b1aa9
doc: Harmonize preformatted in tk1 core
- No unnecessary indentation
- Mark API constants as preformatted
2024-11-15 15:01:31 +01:00
Michael Cardell Widerkrantz
7043521ba9
Move high level system description to README in application_fpga 2024-11-15 15:01:31 +01:00
Michael Cardell Widerkrantz
6e2a77f885
Remove quickstart for the old OSFC dev kit 2024-11-15 15:01:31 +01:00
Jonas Thörnblad
7dc72ade04
Updated application_fpga.bin.sha256 with new hash 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
1b3bae334a
Change "rosc" references to "trng" 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
2364466a9e
Rename rosc.v to trng.v 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
49189a3ba7
Fix typo 2024-11-14 16:35:50 +01:00
Jonas Thörnblad
1ea5db1179
Renamed sb_rgba_drv.v to sb_rgba_drv_sim.v 2024-11-14 16:35:29 +01:00
Jonas Thörnblad
2b89b28b82
Fix small TRNG testbench issues 2024-11-14 11:09:33 +01:00
Daniel Jobson
c4e8f6b6fb
Doc: fix typo of system mode in readme 2024-11-13 14:13:02 +01:00
Daniel Jobson
b90bbea1f6
Remove duplicate entries in default values assignment of tk1 api
cpu_mon_en_we and cdi_mem_we was set twice
2024-11-13 11:16:05 +01:00
Jonas Thörnblad
330146ba3a
Rename top level simulation files
* Rename application_fpga_vsim.v and reset_gen_vsim.v to
  application_fpga_sim.v and reset_gen_sim.v
* Update Makefile
* Fix a typo
2024-11-12 15:33:33 +01:00
Jonas Thörnblad
aea2e319eb
Harmonize the naming of firmware and app mode.
- The API changes name from `_SWITCH_APP` to `_SYSTEM_MODE_CTRL`.
- The registers and wires changes name to `system_mode_*`, instead of a
  mix of `switch_app_*` and `fw_app_mode`.
2024-11-12 15:13:59 +01:00
Daniel Jobson
69ef6dde8b
Remove production_test files
production_test related files are moved out of this repository, since it
relates to production of the hardware and not the fpga construction or
firmware.
2024-10-25 13:20:50 +02:00
Mikael Ågren
a32ecade54
Fix flash target in contrib/Makefile
Setting the working directory to a directory that exist.

Previously the working directory was set to /build/hw/application_fpga.
But that path does not exist since hw/application_fpga was mounted to
/build. Thus resulting in an error:
'Error: workdir "/build/hw/application_fpga" does not exist on
container'
2024-10-25 12:55:27 +02:00
Jonas Thörnblad
c6e8b6930c
Add place and route script
Run multiple threads of nextpnr-ice40 to find a seed that gives a
layout that meets timing.
2024-10-22 15:20:39 +02:00