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Align module name with its file name.
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@ -1,8 +1,8 @@
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//======================================================================
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//
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// reset_gen_sim.v
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// ----------------
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// Reset generator Verilator simulation of the application_fpga.
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// ---------------
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// Reset generator simulation of the application_fpga.
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//
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//
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// Author: Joachim Strombergson
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@ -13,7 +13,7 @@
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`default_nettype none
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module reset_gen #(
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module reset_gen_sim #(
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parameter RESET_CYCLES = 200
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) (
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input wire clk,
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@ -63,8 +63,8 @@ module reset_gen #(
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end
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end
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endmodule // reset_gen
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endmodule // reset_gen_sim
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//======================================================================
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// EOF reset_gen.v
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// EOF reset_gen_sim.v
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//======================================================================
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