Commit Graph

555 Commits

Author SHA1 Message Date
Jonas Thörnblad
fe9055ea23
Add script to split app into simulation ram
Co-authored-by: Mikael Ågren <mikael@tillitis.se>
2024-11-28 16:10:00 +01:00
Jonas Thörnblad
3cd902f792
Add top level testbench for application_fpga_sim.v 2024-11-28 16:10:00 +01:00
Jonas Thörnblad
4260e1d5ac
Update application_fpga_sim.v to match application_fpga.v 2024-11-28 16:10:00 +01:00
Jonas Thörnblad
a330aa15ec
Add verilog file for TRNG simulation 2024-11-28 16:10:00 +01:00
Jonas Thörnblad
d3b9660180
Align module name with its file name. 2024-11-28 16:09:59 +01:00
Jonas Thörnblad
e54045a4dd
Add APP_SIZE parameter to tk1 block to set size of application when simulating. 2024-11-28 16:09:59 +01:00
Daniel Jobson
5b49d80891
tb: make timer core testbench selftesting
- Compare against an expected result and count errors
- Exit with the right error code
- Clean up the output
2024-11-27 08:10:15 +01:00
Daniel Jobson
c735c6fdde
tb: make tb_timer.v selftesting
- Compare against an expected result and count errors
- Exit with the right error code
- Lower write_word() to 1 clk cycle instead of two. It only requires one
  clock cycle to write, otherwise if it is two one have to compensate for it
  in the tests since we are counting cycles.
2024-11-27 08:10:15 +01:00
Daniel Jobson
6bdedf4f86
Fix bug in timer core, where it misses clock cycles
Remove redundant timer state. This fixes a bug where the timer misses a
clock cycle every time the prescaler counter reaches 1. This means if
one uses a large prescaler, like 18E6, it is barely noticeable, but if
one have a low prescaler and a high timer value it becomes significant.
This also yields the running_* registers redundant, which are removed.

Add clarity to the readme.

Update the timer to default to values of one, for prescaler and timer
count.
2024-11-27 08:10:15 +01:00
Daniel Jobson
3d7a97ecbc
fpga: remove the API for configuring the UART core
This removes the possibility to configure the bit rate, data bits and
stop bits at runtime from the API. This reduces the
usage of LCs with ~4%.

It is still possible to configure the core before building.

Update digest of application_fpga.bin.sha256
2024-11-26 15:24:12 +01:00
Jonas Thörnblad
0445c8f993
Add nextpnr flag '--exit-on-failed-target-frequency' 2024-11-22 15:47:42 +01:00
Jonas Thörnblad
08a204dfa6
Minimize number of Dockerfile RUN commands to lower number of
used layers in the image. Too many layers will give an error.
2024-11-22 15:47:41 +01:00
Daniel Jobson
1941a22007
Doc: move implementation details of RAM scrambling to RAM core 2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
de8fcb8768
Remove DCO document 2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
ebd6b17966
Revise top-level README
- Simplify.
- Update links.
- Remove DCO link
2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
86aedcce69
Revise top-level README for the hardware design
Merged information from fpga.md, and hence fpga.md is removed.
2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
9f975bb66f
Add clangd target
Create a compile_commands.json to help clangd for LSP.
2024-11-15 15:01:31 +01:00
Michael Cardell Widerkrantz
fe8f0b1aa9
doc: Harmonize preformatted in tk1 core
- No unnecessary indentation
- Mark API constants as preformatted
2024-11-15 15:01:31 +01:00
Michael Cardell Widerkrantz
7043521ba9
Move high level system description to README in application_fpga 2024-11-15 15:01:31 +01:00
Michael Cardell Widerkrantz
6e2a77f885
Remove quickstart for the old OSFC dev kit 2024-11-15 15:01:31 +01:00
Jonas Thörnblad
7dc72ade04
Updated application_fpga.bin.sha256 with new hash 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
1b3bae334a
Change "rosc" references to "trng" 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
2364466a9e
Rename rosc.v to trng.v 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
49189a3ba7
Fix typo 2024-11-14 16:35:50 +01:00
Jonas Thörnblad
1ea5db1179
Renamed sb_rgba_drv.v to sb_rgba_drv_sim.v 2024-11-14 16:35:29 +01:00
Jonas Thörnblad
2b89b28b82
Fix small TRNG testbench issues 2024-11-14 11:09:33 +01:00
Daniel Jobson
c4e8f6b6fb
Doc: fix typo of system mode in readme 2024-11-13 14:13:02 +01:00
Daniel Jobson
b90bbea1f6
Remove duplicate entries in default values assignment of tk1 api
cpu_mon_en_we and cdi_mem_we was set twice
2024-11-13 11:16:05 +01:00
Jonas Thörnblad
330146ba3a
Rename top level simulation files
* Rename application_fpga_vsim.v and reset_gen_vsim.v to
  application_fpga_sim.v and reset_gen_sim.v
* Update Makefile
* Fix a typo
2024-11-12 15:33:33 +01:00
Jonas Thörnblad
aea2e319eb
Harmonize the naming of firmware and app mode.
- The API changes name from `_SWITCH_APP` to `_SYSTEM_MODE_CTRL`.
- The registers and wires changes name to `system_mode_*`, instead of a
  mix of `switch_app_*` and `fw_app_mode`.
2024-11-12 15:13:59 +01:00
Daniel Jobson
69ef6dde8b
Remove production_test files
production_test related files are moved out of this repository, since it
relates to production of the hardware and not the fpga construction or
firmware.
2024-10-25 13:20:50 +02:00
Mikael Ågren
a32ecade54
Fix flash target in contrib/Makefile
Setting the working directory to a directory that exist.

Previously the working directory was set to /build/hw/application_fpga.
But that path does not exist since hw/application_fpga was mounted to
/build. Thus resulting in an error:
'Error: workdir "/build/hw/application_fpga" does not exist on
container'
2024-10-25 12:55:27 +02:00
Jonas Thörnblad
c6e8b6930c
Add place and route script
Run multiple threads of nextpnr-ice40 to find a seed that gives a
layout that meets timing.
2024-10-22 15:20:39 +02:00
Jonas Thörnblad
8af048fb9a
Add yosys flags to optimize synthesis
* -abc2, run two passes of 'abc' for slightly improved logic density
  * -device u, optimize timing for up5k device
  * -dff, run 'abc'/'abc9' with -dff (D flip flop) option

  Update digest of application_fpga.bin
2024-10-22 12:46:12 +02:00
Jonas Thörnblad
3514d7ef3c
FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
Jonas Thörnblad
e04aacda48
Add make target to format verilog code using verible-verilog-format
Flags:
        --indentation_spaces=2
        --wrap_end_else_clauses=true

Verify flag, used in checkfmt, only returns error if the last file is
not formatted, temporary fix implemented with grep.
2024-10-22 12:04:19 +02:00
Daniel Jobson
70986a1840
Doc: fix broken links, update system_description regarding data and
address randomization and fix typos
2024-10-17 16:21:32 +02:00
Daniel Jobson
1d6830adf7
Swap to a newer picture of the TKey for the readme 2024-10-17 16:21:32 +02:00
Daniel Jobson
559924868e
Move the boards folder to new repositories
To simplify versioning and isolate the different parts of the projects
to their own repositories, these hardware parts are moved to separate
locations.

- tk1, mta1-usb-dev, mta-usb-v1 and mta1-library moves to
  https://github.com/tillitis/tk1-pcba
- tp1, mta1-usb-programmer, mta1-library and KiCad-RP Pico moves to
  https://github.com/tillitis/tp1
- Relevant documentation referring to these boards are also moved to the
  new repositories, links are updated to point to the new location
- The CERN-OHL-S license is removed from this repo
- CI is no longer building the TP1 firmware
2024-10-17 16:21:24 +02:00
Jonas Thörnblad
f66617431b
Update toolchain with new versions of FPGA tools and remove fw/apps/programmer toolschains
- Change docker image to ubuntu 24.04

 - Add new versions of:
	* clang (18.1.3, part of ubuntu 24.04)
	* icestorm (commit 738af822905fdcf0466e9dd784b9ae4b0b34987f)
	* yosys (0.45)
	* nextpnr (0.7) + extra patches for RNG seed handling and early exit
	* iverilog (v12)
	* verilator (v5.028)
	* verible (v0.0-3795)
	* cocotb (v1.9.1)
 - Remove:
	* gcc-arm-none-eabi
	* libnewlib-arm-none-eabi
	* libstdc++-arm-none-eabi-newlib
	* pico-sdk
	* golang
2024-10-16 18:43:29 +02:00
Jonas Thörnblad
9e57296d91
Include SPI master in default build
This prevents building without the SPI master, the intention is to use
a different method than if-defs, but it will be introduced at a later
stage.
2024-10-16 12:50:32 +02:00
Daniel Jobson
cbb2ba7512
Doc: fix typo in tk1 core readme 2024-10-11 15:50:07 +02:00
Daniel Jobson
d9d41811bd
tb: fix tk1 testbench after name change
This issue was introduced in commit 53c5e707, after name change of RAM
randomization API.
2024-10-11 15:50:07 +02:00
Daniel Jobson
056ee4d3ee
Add make target to clean testbench files
Add it as default in the contrib Makefile.
2024-10-11 15:50:07 +02:00
Daniel Jobson
f13366538e
fw: Fix erroneous type in frame header 2024-10-09 15:52:00 +02:00
Jonas Thörnblad
0ea0eeb967
Fix makefile lines and tee exit status problem
* Break long lines and use tab to indent
* Remove use of "tee" since it messes up the return status
* Remove the generated application_fpga_par.json if nextpnr-ice40 fails
  on timing.
* Change log file ending from .log to .txt
* Fix some spacing
2024-10-08 16:07:17 +02:00
Daniel Jobson
bf1ac5c237
Remove YosysHQ copyright and fix name typo
The removal is coordinated and approved by YosysHQ, and are removed
to keep our headers uniform. These files were written on behalf of
Tillitis.
Two typos was corrected as well.
2024-09-30 15:01:31 +02:00
Daniel Jobson
81950ef7b2
fw: remove warning of missing prototypes when building with QEMU console
enabled.
2024-09-19 16:52:04 +02:00
Daniel Jobson
613316f53e
fw: simplify how to enable QEMU debug in firmware.
- Remove the define `NOCONSOLE`, add define `QEMU_CONSOLE`
- Inverse the use of it, add the define to have QEMU debug output in fw.
- Add a make target `qemu_firmware.elf` which builds the firmware with
  QEMU console enabled.

Co-authored-by: Mikael Ågren <mikael@tillitis.se>
2024-09-19 16:51:55 +02:00
Joachim Strömbergson
35052e50cb
FPGA: Move RAM address and data scrambling into the RAM module.
Move the logic implementing the RAM address and data
	scrambling, descrambling into the RAM module. This cleans up
	the top level, and makes it easier to change the scrambling
	without chaning the top. In order to do correct scrambling the
	address to the RAM core must be 16 bits, not 15.

	Clean up some minor details at the top level, fixing text
        aligment and grouping of ports in instances.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-30 10:53:13 +02:00