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338 Commits 33 Branches 14 Tags 31 MiB
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47 Commits

Author SHA1 Message Date
Joachim Strömbergson
000b7644b5
Update fw ram last address to match new mem size 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-08 13:31:45 +01:00
Joachim Strömbergson
2e2ca04ab7
Bump FPGA design version to 5 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-07 12:30:10 +01:00
Joachim Strömbergson
d075cc72c3
Manually merged changes for scrambling 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-07 10:42:59 +01:00
Joachim Strömbergson
3eb5b7879c Add API address to read out number of bytes in Rx FIFO 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-07 08:22:27 +01:00
Joachim Strömbergson
4db4e39205
Clarify the purpose and functionality of the tk1 core 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-07 08:20:18 +01:00
Joachim Strömbergson
6f327d2ff9
Block changing of monitor addresses when enabled 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:55 +01:00
Joachim Strömbergson
66ebe5089a
Add fw_ram as always active exe monitor area 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:55 +01:00
Joachim Strömbergson
5c05ae657e
exe monitor can only be enabled, not disabled 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:55 +01:00
Joachim Strömbergson
7612d00ccf
Feed CPU illegal instruction to trigger trap 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:55 +01:00
Joachim Strömbergson
86ea45e10a
Add CPU execution monitor 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:53 +01:00
Joachim Strömbergson
e514f778b2 Remove stray variable for blake2s address update 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 11:32:38 +01:00
Joachim Strömbergson
adcccc44de Change reset value for the trap led to black 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 11:32:38 +01:00
Joachim Strömbergson
d335dd708a Add HW to detect trap in cpu and signal using the LEDs 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 11:32:38 +01:00
Joachim Strömbergson
caeee54e19
Change LED reset value to black 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-02-27 13:21:51 +01:00
Joachim Strömbergson
6137b88fe0 Add separate start, stop bits and running status bit in API 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-01-30 15:48:57 +01:00
Joachim Strömbergson
f020495695
Cleanup of tb for timer core 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-01-20 10:14:44 +01:00
Joachim Strömbergson
9ce2b8a84a
Only accept tx data when the core is ready 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-01-02 13:10:40 +01:00
Joachim Strömbergson
5c74a0727c
Lock down access to UDI in app mode 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2022-12-20 12:05:56 +01:00
Joachim Strömbergson
a48dc7cbbb
Add reg writable from FW, readable from app for blake2s entry 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2022-12-08 16:16:15 +01:00
Daniel Lublin
49d4735f17
Use TKey name 
Signed-off-by: Daniel Lublin <daniel@lublin.se>
 2022-12-02 08:03:06 +01:00
Joachim Strömbergson
8061491f6e
Cleanup, and use fifo_empty to indicate data available 2022-10-28 13:12:47 +02:00
Joachim Strömbergson
24d8680772
Improve detection of empty and full FIFO 2022-10-28 13:09:21 +02:00
Joachim Strömbergson
0eacbca2f9
Increase size of RX-FIFO to 512 bytes 2022-10-28 12:48:13 +02:00
Daniel Lublin
4b4f014d38
Rename to TK1 2022-10-26 09:20:02 +02:00
Daniel Lublin
675fa1087f
Raise bps to 62500 2022-10-21 14:10:41 +02:00
Joachim Strömbergson
19b75e71fe
Fix bit counter and simplify emtropy extraction 2022-10-19 13:10:26 +02:00
Joachim Strömbergson
c07c15a8b8
Update README to describe the new ROSC based TRNG 2022-10-19 09:37:58 +02:00
Joachim Strömbergson
ddd969870e
Count from init values to one, not zero 2022-10-18 11:06:40 +02:00
Joachim Strömbergson
f6046d55a9
Change ADDR_CTRL to be a pulsed start_stop signal 2022-10-14 08:50:30 +02:00
Joachim Strömbergson
c3f7c5fb06
Ignore the prescaler if prescaler init value is zero 2022-10-13 16:24:03 +02:00
Joachim Strömbergson
2be934ee22
Restore start and stop bits, but clarify in documenation 2022-10-13 16:10:08 +02:00
Joachim Strömbergson
00d180d34e
Change to a single run bit and update access control 2022-10-13 14:58:39 +02:00
Joachim Strömbergson
1b03459ab3
Remove app-accessible debug register from mta1 core 2022-10-13 13:51:19 +02:00
Joachim Strömbergson
5013338e50
Change to a more descriptive name 2022-10-12 11:14:46 +02:00
Joachim Strömbergson
a9fd26da3b
Fix bit bit width mismatches 2022-10-12 10:21:50 +02:00
Joachim Strömbergson
82a64f2b2c
Remove DONE state that added one extra final cycle 2022-10-12 10:06:41 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG 2022-10-11 13:17:04 +02:00
Joachim Strömbergson
af36a40f3e Merge branch 'new_trng' 2022-10-11 13:00:13 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores 
timer
       touch_sense
       figaro
       uart
       uds
 2022-10-11 09:50:45 +02:00
Joachim Strömbergson
cdbe71d40d
Add new ROSC based TRNG with VN decorrelation 2022-10-11 08:45:06 +02:00
Joachim Strömbergson
4ed27b4460
Add new rosc based entropy source 2022-10-08 18:37:48 +02:00
Joachim Strömbergson
c90771fe19
Remove API access to current prescaler value 2022-10-06 15:56:13 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following: 
Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
 2022-10-06 13:23:30 +02:00
Joachim Strömbergson
f41573cc60
Update bit counter to match 18 MHz clock frequency 2022-09-30 10:04:37 +02:00
Joachim Strömbergson
610522201b
Remove AXI and WB interface modules 2022-09-27 09:48:54 +02:00
Joachim Strömbergson
3110d1218d
Silence lint re missing pins on cell instances 2022-09-19 10:35:49 +02:00
Joachim Strömbergson
715de60f4a Make initial public release 2022-09-19 08:51:11 +02:00