Commit Graph

10 Commits

Author SHA1 Message Date
Jonas Thörnblad
aea2e319eb
Harmonize the naming of firmware and app mode.
- The API changes name from `_SWITCH_APP` to `_SYSTEM_MODE_CTRL`.
- The registers and wires changes name to `system_mode_*`, instead of a
  mix of `switch_app_*` and `fw_app_mode`.
2024-11-12 15:13:59 +01:00
Jonas Thörnblad
3514d7ef3c
FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
Daniel Lublin
4b4f014d38
Rename to TK1 2022-10-26 09:20:02 +02:00
Daniel Lublin
675fa1087f
Raise bps to 62500 2022-10-21 14:10:41 +02:00
Joachim Strömbergson
cc59d8dc93
Update verilator top level module to match rom module changes 2022-10-06 13:59:01 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following:
Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
2022-10-06 13:23:30 +02:00
Daniel Lublin
2bb62af183
Update bit divisor calc in verilator's uart to our current 18 MHz 2022-10-03 13:11:53 +02:00
Joachim Strömbergson
b2ca3f2ea0
Fix Verilator sim by adding separate reset generator 2022-10-03 12:55:24 +02:00
Daniel Lublin
10b7951933
Let verilator print when touched by kill -USR1 2022-09-21 11:25:13 +02:00
Joachim Strömbergson
715de60f4a Make initial public release 2022-09-19 08:51:11 +02:00