Joachim Strömbergson c35e7680ea Squashed commit of the following: ... Silence lint on intentional combinatinal loops Use better instance names, and a single lint pragma for all macros Remove unused pointer update signals Silence lint on wires where not all bits are used Change fw_app_mode to be an input port to allow access control Remove redundant, unused wire mem_busy Add lint pragma to ignore debug register only enabled by a define Remove clk and reset_n ports from the ROM Adding note and lint pragma for rom address width Fix incorrect register widths in uart_core Assign all 16 bits in LUT config Silence lint warnings on macro instances Correct bit extraction for core addresses to be eight bits wide Correct the bit width of cdi_mem_we wire Add specific output file for logging lint issues Correct bit width of tmp_ready to match one bit ready port		2022-10-06 13:23:30 +02:00
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application_fpga_verilator.cc	Update bit divisor calc in verilator's uart to our current 18 MHz	2022-10-03 13:11:53 +02:00
application_fpga_vsim.v	Squashed commit of the following:	2022-10-06 13:23:30 +02:00
reset_gen_vsim.v	Fix Verilator sim by adding separate reset generator	2022-10-03 12:55:24 +02:00