10 Commits

Author	SHA1	Message	Date
blaufish	426b56ebf5	Verilog 2001 rule; use wires for assignments, not registers. (#139)	2023-08-16 10:44:18 +02:00
Joachim Strömbergson	b9c415f5d6	bank1 access should also be disabled by default. ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-03-13 12:43:07 +01:00
Daniel Lublin	5f4f5c6584	Correct for new fw-ram size ... Signed-off-by: Daniel Lublin <daniel@lublin.se>	2023-03-08 12:34:34 +01:00
Joachim Strömbergson	a63ba8eb13	Double the size of the fw_ram to 2 kByte ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-03-08 11:20:38 +01:00
Joachim Strömbergson	ab03ebd12c	Improve wording ans size info in header ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-01-30 13:19:01 +01:00
Joachim Strömbergson	cc464e5be2	The memory is 256 x 32 bits, not 512 x 32 bits ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-01-30 13:00:43 +01:00
Joachim Strömbergson	159b20fa4e	Zero extend the address to match SB_RAM4K ports	2022-11-09 15:05:03 +01:00
Joachim Strömbergson	8e493b6322	Debug fw_ram and add fw_app_mode access control	2022-10-13 13:14:10 +02:00
Joachim Strömbergson	cbf1104fed	Write whole byte, not nybbles	2022-10-11 17:05:21 +02:00
Joachim Strömbergson	a51619e5b7	Add fw_ram module	2022-10-11 16:58:26 +02:00