mirror of
https://github.com/tillitis/tillitis-key1.git
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93 lines
2.4 KiB
Verilog
93 lines
2.4 KiB
Verilog
//======================================================================
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//
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// fw_ram.v
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// --------
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// A small 512 x 32 RAM for FW use. With support for access control.
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module fw_ram(
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input wire clk,
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input wire reset_n,
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input wire fw_app_mode,
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input wire cs,
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input wire [3 : 0] we,
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input wire [7 : 0] address,
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input wire [31 : 0] write_data,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Registers and wires.
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//----------------------------------------------------------------
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reg ready_reg;
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//----------------------------------------------------------------
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// Concurrent assignment of ports.
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//----------------------------------------------------------------
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assign ready = ready_reg;
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//----------------------------------------------------------------
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// Block RAM instances.
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//----------------------------------------------------------------
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SB_RAM40_4K fw_ram0(
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.RDATA(read_data[15:0]),
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.RADDR(address),
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.RCLK(clk),
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.RCLKE(1'h1),
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.RE(cs),
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.WADDR(address),
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.WCLK(clk),
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.WCLKE(1'h1),
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.WDATA(write_data[15:0]),
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.WE(|we),
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.MASK({{4{we[1]}}, {4{we[0]}}})
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);
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SB_RAM40_4K fw_ram1(
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.RDATA(read_data[31:16]),
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.RADDR(address),
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.RCLK(clk),
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.RCLKE(1'h1),
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.RE(cs),
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.WADDR(address),
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.WCLK(clk),
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.WCLKE(1'h1),
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.WDATA(write_data[31:16]),
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.WE(|we),
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.MASK({{4{we[3]}}, {4{we[2]}}})
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);
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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if (!reset_n) begin
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ready_reg <= 1'h0;
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end
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else begin
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ready_reg <= cs;
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end
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end
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endmodule // fw_ram
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//======================================================================
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// EOF fw_ram.v
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//======================================================================
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