Commit Graph

18 Commits

Author SHA1 Message Date
Joachim Strömbergson
a63ba8eb13
Double the size of the fw_ram to 2 kByte
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-08 11:20:38 +01:00
Joachim Strömbergson
d075cc72c3
Manually merged changes for scrambling
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-07 10:42:59 +01:00
Joachim Strömbergson
74fd7e3001
Fix spelling nits
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-07 08:16:42 +01:00
Joachim Strömbergson
7612d00ccf
Feed CPU illegal instruction to trigger trap
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-06 15:41:55 +01:00
Joachim Strömbergson
8ba97e16f3
Move force_jump function to top level mem system
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-06 15:41:54 +01:00
Joachim Strömbergson
86ea45e10a
Add CPU execution monitor
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-06 15:41:53 +01:00
Joachim Strömbergson
d335dd708a Add HW to detect trap in cpu and signal using the LEDs
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-06 11:32:38 +01:00
Joachim Strömbergson
317561ad32
Remove options that are the same as the default values
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-02-27 10:22:04 +01:00
Joachim Strömbergson
2fa1ffb8e7
Disable HW support in CPU for DIV
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2022-11-28 16:15:01 +01:00
Daniel Lublin
4b4f014d38
Rename to TK1 2022-10-26 09:20:02 +02:00
Joachim Strömbergson
a51619e5b7
Add fw_ram module 2022-10-11 16:58:26 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG 2022-10-11 13:17:04 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following:
Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
2022-10-06 13:23:30 +02:00
Joachim Strömbergson
1aa2d7bd95 Merge branch 'pll' 2022-09-30 10:06:48 +02:00
Joachim Strömbergson
f09ff87f9e
Support DIV instructions and catch illegal instructions 2022-09-28 10:29:00 +02:00
Joachim Strömbergson
90a57c4948
Use PLL and global buffer to increas clock speed 2022-09-27 16:41:38 +02:00
Joachim Strömbergson
3110d1218d
Silence lint re missing pins on cell instances 2022-09-19 10:35:49 +02:00
Joachim Strömbergson
715de60f4a Make initial public release 2022-09-19 08:51:11 +02:00