Jonas Thörnblad
1b3bae334a
Change "rosc" references to "trng"
2024-11-14 16:35:51 +01:00
Jonas Thörnblad
2364466a9e
Rename rosc.v to trng.v
2024-11-14 16:35:51 +01:00
Jonas Thörnblad
2b89b28b82
Fix small TRNG testbench issues
2024-11-14 11:09:33 +01:00
Jonas Thörnblad
3514d7ef3c
FPGA: Format verilog code
2024-10-22 12:04:19 +02:00
Joachim Strömbergson
e961f46e79
Update Verilog version to 2005 for linting
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-04-24 08:44:08 +02:00
Joachim Strömbergson
de668a0244
Clean up code and silence warnings after linting
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-03-20 16:39:53 +01:00
Joachim Strömbergson
17ddb1f84a
Minor fix of ackronyms in the README
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:29 +02:00
Joachim Strömbergson
3e75818879
Fix spelling of toolruns dir
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:29 +02:00
Joachim Strömbergson
5e34802d1c
Update readme with info on API, status, usage and performance
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:28 +02:00
Joachim Strömbergson
361381210e
Add an initial testcase. Hard to simulate entropy
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:28 +02:00
Joachim Strömbergson
a76fc19c65
Add Makefile, testbench and support module needed to build som target
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:28 +02:00
Daniel Lublin
49d4735f17
Use TKey name
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Signed-off-by: Daniel Lublin <daniel@lublin.se>
2022-12-02 08:03:06 +01:00
Joachim Strömbergson
19b75e71fe
Fix bit counter and simplify emtropy extraction
2022-10-19 13:10:26 +02:00
Joachim Strömbergson
c07c15a8b8
Update README to describe the new ROSC based TRNG
2022-10-19 09:37:58 +02:00
Joachim Strömbergson
5013338e50
Change to a more descriptive name
2022-10-12 11:14:46 +02:00
Joachim Strömbergson
a9fd26da3b
Fix bit bit width mismatches
2022-10-12 10:21:50 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG
2022-10-11 13:17:04 +02:00
Joachim Strömbergson
af36a40f3e
Merge branch 'new_trng'
2022-10-11 13:00:13 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores
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timer
touch_sense
figaro
uart
uds
2022-10-11 09:50:45 +02:00
Joachim Strömbergson
cdbe71d40d
Add new ROSC based TRNG with VN decorrelation
2022-10-11 08:45:06 +02:00
Joachim Strömbergson
4ed27b4460
Add new rosc based entropy source
2022-10-08 18:37:48 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following:
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Silence lint on intentional combinatinal loops
Use better instance names, and a single lint pragma for all macros
Remove unused pointer update signals
Silence lint on wires where not all bits are used
Change fw_app_mode to be an input port to allow access control
Remove redundant, unused wire mem_busy
Add lint pragma to ignore debug register only enabled by a define
Remove clk and reset_n ports from the ROM
Adding note and lint pragma for rom address width
Fix incorrect register widths in uart_core
Assign all 16 bits in LUT config
Silence lint warnings on macro instances
Correct bit extraction for core addresses to be eight bits wide
Correct the bit width of cdi_mem_we wire
Add specific output file for logging lint issues
Correct bit width of tmp_ready to match one bit ready port
2022-10-06 13:23:30 +02:00
Joachim Strömbergson
3110d1218d
Silence lint re missing pins on cell instances
2022-09-19 10:35:49 +02:00
Joachim Strömbergson
715de60f4a
Make initial public release
2022-09-19 08:51:11 +02:00
