Joachim Strömbergson
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90a57c4948
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Use PLL and global buffer to increas clock speed
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2022-09-27 16:41:38 +02:00 |
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Joachim Strömbergson
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610522201b
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Remove AXI and WB interface modules
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2022-09-27 09:48:54 +02:00 |
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Daniel Lublin
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10b7951933
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Let verilator print when touched by kill -USR1
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2022-09-21 11:25:13 +02:00 |
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Daniel Lublin
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8066c1092e
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Make fmt output changes that will be made
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2022-09-21 10:13:39 +02:00 |
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Björn Töpel
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2f59eaacdc
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Add default values to tpt.py
Provide default values for vendor id, product id, revision number, and
serial number.
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2022-09-21 09:49:07 +02:00 |
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Joachim Strömbergson
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43ec0641c0
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Change uss to ent to remove confusion
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2022-09-21 09:38:44 +02:00 |
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Daniel Lublin
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40803993e1
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Make synth.json depend on data/{uds,udi}.hex; revise docs
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2022-09-20 16:37:04 +02:00 |
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Joachim Strömbergson
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9d5e1c5ad5
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Remove debug output of arguments
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2022-09-19 12:37:27 +02:00 |
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Joachim Strömbergson
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3110d1218d
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Silence lint re missing pins on cell instances
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2022-09-19 10:35:49 +02:00 |
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Joachim Strömbergson
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715de60f4a
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Make initial public release
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2022-09-19 08:51:11 +02:00 |
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