Commit Graph

10 Commits

Author SHA1 Message Date
Joachim Strömbergson
5013338e50
Change to a more descriptive name 2022-10-12 11:14:46 +02:00
Joachim Strömbergson
a9fd26da3b
Fix bit bit width mismatches 2022-10-12 10:21:50 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG 2022-10-11 13:17:04 +02:00
Joachim Strömbergson
af36a40f3e Merge branch 'new_trng' 2022-10-11 13:00:13 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores
timer
       touch_sense
       figaro
       uart
       uds
2022-10-11 09:50:45 +02:00
Joachim Strömbergson
cdbe71d40d
Add new ROSC based TRNG with VN decorrelation 2022-10-11 08:45:06 +02:00
Joachim Strömbergson
4ed27b4460
Add new rosc based entropy source 2022-10-08 18:37:48 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following:
Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
2022-10-06 13:23:30 +02:00
Joachim Strömbergson
3110d1218d
Silence lint re missing pins on cell instances 2022-09-19 10:35:49 +02:00
Joachim Strömbergson
715de60f4a Make initial public release 2022-09-19 08:51:11 +02:00