Joachim Strömbergson 3bc2453287

A construction of a minimal SPI master. ...

- NOTE: This is an optional feature, not built by default. Not included
  in the tk1 for sale at Tillitis shop.
- This makes it possible to interface the SPI flash onboard TKey.
- To include the SPI master in the build, use `make application_fpga.bin
  YOSYS_FLAG=-DINCLUDE_SPI_MASTER`.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

2024-06-11 15:28:29 +02:00

..

application_fpga.v

A construction of a minimal SPI master.

2024-06-11 15:28:29 +02:00

clk_reset_gen.v

Explain how we attain 18 MHz

2022-10-21 14:33:03 +02:00

fw_ram.v

Verilog 2001 rule; use wires for assignments, not registers. (#139)

2023-08-16 10:44:18 +02:00

ram.v

Implement cs0 and cs1 as logic equations, not muxes

2024-03-20 14:36:55 +01:00

rom.v

Clean up code and silence warnings after linting

2024-03-20 16:39:53 +01:00