Mikael Ågren 7554787678 fpga: Add extra access control on UDS ... Restrict access to UDS when we have exited firmware the first time. Co-authored-by: Michael Cardell Widerkrantz <mc@tillitis.se>		2025-02-27 14:35:22 +01:00
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clk_reset_gen	fpga/testfw: Update clock frequency to 24 MHz	2025-02-11 13:50:04 +01:00
fw_ram	fpga/fw: Rename system_mode to app_mode	2025-02-27 14:20:37 +01:00
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
ram	Doc: move implementation details of RAM scrambling to RAM core	2024-11-20 15:48:49 +01:00
rom	Fix typo	2024-11-14 16:35:50 +01:00
timer	tb: make timer core testbench selftesting	2024-11-27 08:10:15 +01:00
tk1	fpga: Add extra access control on UDS	2025-02-27 14:35:22 +01:00
touch_sense	tb: Make touch_sense selftesting	2024-12-09 13:55:42 +01:00
trng	tb: Make trng selftesting	2024-12-09 13:55:43 +01:00
uart	fpga: Format Verilog	2025-02-11 14:37:29 +01:00
uds	fpga: Add extra access control on UDS	2025-02-27 14:35:22 +01:00