Mikael Ågren 5e15b40a86 PoC: PicoRV32 interrupts ... A proof-of-concept of enabling PicoRV32 interrupts. Two interrupt sources, which can be triggered by writes to memory addresses, are added. The design has only been simulated, not run on hardware. Synthesis: Ice40 LC utilization is 93% (4934/5280) when built using tkey-builder:4 Simulation: A `tb_application_fpga_irqpoc` target is added. Running `make tb_application_fpga_irqpoc` creates `tb_application_fpga_sim.fst` which can be inspected in GTKWave or Surfer. Firmware: A simple firmware is added in `fw/irqpoc`. It enables both interrupts and triggers each interrupt once. Custom PicoRV32 instructions are located in `custom_ops.S`. It is imported from upstream PicoRV32 commit: 70f3c33ac8		2025-02-12 11:08:15 +01:00
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clk_reset_gen	fpga/testfw: Update clock frequency to 24 MHz	2025-02-11 13:50:04 +01:00
fw_ram	Doc: fix typo of system mode in readme	2024-11-13 14:13:02 +01:00
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
ram	Doc: move implementation details of RAM scrambling to RAM core	2024-11-20 15:48:49 +01:00
rom	Fix typo	2024-11-14 16:35:50 +01:00
timer	tb: make timer core testbench selftesting	2024-11-27 08:10:15 +01:00
tk1	PoC: PicoRV32 interrupts	2025-02-12 11:08:15 +01:00
touch_sense	tb: Make touch_sense selftesting	2024-12-09 13:55:42 +01:00
trng	tb: Make trng selftesting	2024-12-09 13:55:43 +01:00
uart	fpga: Format Verilog	2025-02-11 14:37:29 +01:00
uds	Harmonize the naming of firmware and app mode.	2024-11-12 15:13:59 +01:00