Joachim Strömbergson 53c5e70795 FPGA: Update names for RAM randomization API ... Update: - README - testbench - Symbolic names and variables in fw - registers - port name and wires - Update fpga and fw digests Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-07-10 13:45:26 +02:00
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application_fpga.v	FPGA: Update names for RAM randomization API	2024-07-10 13:45:26 +02:00
clk_reset_gen.v	Explain how we attain 18 MHz	2022-10-21 14:33:03 +02:00
fw_ram.v	Verilog 2001 rule; use wires for assignments, not registers. (#139)	2023-08-16 10:44:18 +02:00
ram.v	Implement cs0 and cs1 as logic equations, not muxes	2024-03-20 14:36:55 +01:00
rom.v	Clean up code and silence warnings after linting	2024-03-20 16:39:53 +01:00