Mikael Ågren 4a27940bf1 PoC: tb: Fix tb_tk1 test10 (SPI loop back test) ... Fix test10. It broke while implementing interrupt based syscalls. Cleaning up after the previous test. We reset the memory bus to a known idle state. We also reset the DUT to make the SPI master visible.		2025-02-12 11:08:31 +01:00
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clk_reset_gen	fpga/testfw: Update clock frequency to 24 MHz	2025-02-11 13:50:04 +01:00
fw_ram	PoC: Control access to FW RAM	2025-02-12 11:08:26 +01:00
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
ram	Doc: move implementation details of RAM scrambling to RAM core	2024-11-20 15:48:49 +01:00
rom	Fix typo	2024-11-14 16:35:50 +01:00
timer	tb: make timer core testbench selftesting	2024-11-27 08:10:15 +01:00
tk1	PoC: tb: Fix tb_tk1 test10 (SPI loop back test)	2025-02-12 11:08:31 +01:00
touch_sense	tb: Make touch_sense selftesting	2024-12-09 13:55:42 +01:00
trng	tb: Make trng selftesting	2024-12-09 13:55:43 +01:00
uart	fpga: Format Verilog	2025-02-11 14:37:29 +01:00
uds	PoC: Make sensitive assets only readable/writable before system_mode is set	2025-02-12 11:08:27 +01:00