Joachim Strömbergson c0a79e77c6

fpga: Add stateful access control ...

Add access stateful control register that toggles if access to a
      resources is granted based on if code is excuted from ROM or RAM.
      The register is used to enable or block access to SPI but
      potentially other HW resources.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

2024-08-22 11:29:44 +02:00

..

application_fpga.v

fpga: Add stateful access control

2024-08-22 11:29:44 +02:00

clk_reset_gen.v

FPGA: Increase clock frequency to 21 MHz

2024-08-20 13:45:00 +02:00

fw_ram.v

Verilog 2001 rule; use wires for assignments, not registers. (#139)

2023-08-16 10:44:18 +02:00

ram.v

Implement cs0 and cs1 as logic equations, not muxes

2024-03-20 14:36:55 +01:00

rom.v

Clean up code and silence warnings after linting

2024-03-20 16:39:53 +01:00