Daniel Jobson 833bf63bc8 PoC: Make sensitive assets only readable/writable before system_mode is set ... After the first time system_mode is set to one, the assets will no longer be read- or writeable, even if system_mode is set to zero at a later syscall. This is to make sure syscalls does not have the same privilege as the firmware has at first boot. We need to monitor when system_mode is set to one, otherwise we might accedentially lock the assets before actually leaving firmware, for example if firmware would use a function set in any of the registers used in system_mode_ctrl. Co-authored-by: Mikael Ågren <mikael@tillitis.se>		2025-02-12 11:08:27 +01:00
..
clk_reset_gen	fpga/testfw: Update clock frequency to 24 MHz	2025-02-11 13:50:04 +01:00
fw_ram	PoC: Control access to FW RAM	2025-02-12 11:08:26 +01:00
picorv32
ram
rom
timer
tk1	PoC: Make sensitive assets only readable/writable before system_mode is set	2025-02-12 11:08:27 +01:00
touch_sense
trng
uart	fpga: Format Verilog	2025-02-11 14:37:29 +01:00
uds	PoC: Make sensitive assets only readable/writable before system_mode is set	2025-02-12 11:08:27 +01:00