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1e20dba10a
The FPGA uwg30 package cannot use B3 as an input when an instance of SB_PLL40_CORE is placed. We swap fpga_cts and ch552_cts to make B3 (from here on fpga_cts) an output. For more info check out: FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf chapter "5.1 PLL Placement Rules"
21 lines
418 B
C
21 lines
418 B
C
// SPDX-FileCopyrightText: 2024 Tillitis AB <tillitis.se>
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// SPDX-License-Identifier: MIT
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#ifndef __GPIO_H__
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#define __GPIO_H__
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#include <stdint.h>
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#define PIN_P1_4 0x10
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#define PIN_P1_5 0x20
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#define PIN_FPGA_CTS PIN_P1_5
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#define PIN_CH552_CTS PIN_P1_4
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void gpio_set(uint8_t pin);
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void gpio_unset(uint8_t pin);
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uint8_t gpio_get(uint8_t pin);
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void gpio_dir_in(uint8_t pin);
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void gpio_dir_out(uint8_t pin);
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#endif
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