4 commits

Author	SHA1	Message	Date
Mikael Ågren	1e20dba10a	fpga/ch552: Swap fpga_cts and ch552_cts pins ... The FPGA uwg30 package cannot use B3 as an input when an instance of SB_PLL40_CORE is placed. We swap fpga_cts and ch552_cts to make B3 (from here on fpga_cts) an output. For more info check out: FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf chapter "5.1 PLL Placement Rules"	2025-05-19 08:55:26 +02:00
Mikael Ågren	45af9146d6	ch552: Make CTS pins configurable	2025-05-19 08:55:26 +02:00
Michael Cardell Widerkrantz	7eca72c2c3	ch552: Add SPDX tags ... - Add SPDX tags to source files. - Make REUSE compliant. - Add reuse.toml configuration.	2025-04-07 11:00:31 +02:00
Jonas Thörnblad	d94387a9e7	ch552: Split functionality into separate files ... - Move GPIO functions to gpio.c and gpio.h - Move string handling functions for debug to lib.c and lib.h - Add config.h and move config defines there - Add debug print functionality via FPGA with framing protocol - Add Flash Code and Flash Data functions to flash.c and flash.h	2025-04-07 11:00:11 +02:00