blaufish 426b56ebf5 Verilog 2001 rule; use wires for assignments, not registers. (#139)		2023-08-16 10:44:18 +02:00
..
application_fpga.v	Double the size of the fw_ram to 2 kByte	2023-03-08 11:20:38 +01:00
clk_reset_gen.v	Explain how we attain 18 MHz	2022-10-21 14:33:03 +02:00
fw_ram.v	Verilog 2001 rule; use wires for assignments, not registers. (#139)	2023-08-16 10:44:18 +02:00
ram.v	Make initial public release	2022-09-19 08:51:11 +02:00
rom.v	Move force_jump function to top level mem system	2023-03-06 15:41:54 +01:00