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tillitis-key/hw/application_fpga
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Michael Cardell Widerkrantz 0590445f3d
Add testbench targets on top-level 
The testbenches live in their own Makefiles under
hw/application_fpga/core/*/toolruns (except picorv32). Let's add a
top-level target to build and run them.

In order to run core testbenches, use

  cd hw/application_fpga
  make tb

or if using Podman:

  cd contrib
  make run-tb

to run the same target in a container.
2024-03-20 13:47:12 +01:00
..
core Explicity make uart_core.rx_data a wire (#140) 2023-08-16 10:43:04 +02:00
data Change name of pin constraint file to match tk1 pcb 2023-07-04 09:04:29 +02:00
fw fw: Change ASLR name in MMIO 2024-03-19 14:36:31 +01:00
rtl Verilog 2001 rule; use wires for assignments, not registers. (#139) 2023-08-16 10:44:18 +02:00
tb Rename to TK1 2022-10-26 09:20:02 +02:00
tools Correct to new path 2023-01-13 15:42:46 +01:00
application_fpga.bin.sha256 FW: Force the CPU to hang on errors 2024-03-14 15:48:10 +01:00
config.vlt Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal 2023-03-01 13:37:31 +01:00
firmware.bin.sha512 FW: Force the CPU to hang on errors 2024-03-14 15:48:10 +01:00
Makefile Add testbench targets on top-level 2024-03-20 13:47:12 +01:00