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Add testbench targets on top-level

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The testbenches live in their own Makefiles under
hw/application_fpga/core/*/toolruns (except picorv32). Let's add a
top-level target to build and run them.

In order to run core testbenches, use

  cd hw/application_fpga
  make tb

or if using Podman:

  cd contrib
  make run-tb

to run the same target in a container.
This commit is contained in:
Michael Cardell Widerkrantz 2024-03-20 12:15:38 +01:00 committed by dehanj
parent ea9271292c
commit 0590445f3d
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GPG Key ID: 3707A9DBF4BB8F1A
2 changed files with 25 additions and 1 deletions
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7
contrib/Makefile
View File

@ -1,3 +1,5 @@
# Copyright (C) 2024 - Tillitis AB
# SPDX-License-Identifier: GPL-2.0-only
# image produced by build-image targets
BUILDIMAGE=tkey-builder-local
@ -9,6 +11,7 @@ all:
@echo "Targets:"
@echo "run Run a shell using image '$(IMAGE)' (Podman)"
@echo "run-make Build the FPGA bitstream using image '$(IMAGE)' (Podman)"
@echo "run-tb Run all the testbenches using image '$(IMAGE)' (Podman)"
@echo "run-make-no-clean Like run-make but without cleaning first, useful for iterative firmware dev"
@echo "run-make-clean_fw Like run-make but cleans only firmware"
@echo "flash Program the SPI flash on the TKey - needs an existing bitstream"
@ -30,6 +33,10 @@ run-make:
podman run --rm --mount type=bind,source="`pwd`/../hw/application_fpga",target=/build -w /build -it \
$(IMAGE) make clean application_fpga.bin
run-tb:
podman run --rm --mount type=bind,source="`pwd`/../hw/application_fpga",target=/build -w /build -it \
$(IMAGE) make tb
run-make-testfw:
podman run --rm --mount type=bind,source="`pwd`/../hw/application_fpga",target=/build -w /build -it \
$(IMAGE) make clean application_fpga_testfw.bin

19
hw/application_fpga/Makefile
View File

@ -6,9 +6,13 @@
# HW targets as well as its firmware.
#
#
# Copyright (C) 2022, 2023 - Tillitis AB
# Copyright (C) 2022-2024 - Tillitis AB
# SPDX-License-Identifier: GPL-2.0-only
#
#
# Please note: When creating a new cores and adding more testbenches,
# please update the tb target below to include it as well.
#
#=======================================================================
#-------------------------------------------------------------------
@ -207,6 +211,18 @@ verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS)
make -C verilated -f Vapplication_fpga.mk
.PHONY: verilator
#-------------------------------------------------------------------
# Run all testbenches
#-------------------------------------------------------------------
tb:
make -C core/timer/toolruns sim-top
make -C core/tk1/toolruns sim-top
make -C core/touch_sense/toolruns sim-top
make -C core/trng/toolruns sim-top
make -C core/uart/toolruns sim-top
make -C core/uds/toolruns sim-top
.PHONY: tb
#-------------------------------------------------------------------
# Main FPGA build flow.
@ -333,6 +349,7 @@ help:
@echo "bram_fw.hex Build a fake BRAM file that will be filled in later after place-n-route."
@echo "verilator Build Verilator simulation program"
@echo "lint Run lint on Verilog source files."
@echo "tb Run all testbenches"
@echo "prog_flash Program device flash with FGPA bitstream including firmware (using the RPi Pico-based programmer)."
@echo "prog_flash_testfw Program device flash as above, but with testfw."
@echo "clean Delete all generated files."