Daniel Jobson
a37f687881
Change license to BSD-2-Clause
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This was announced on the Tillitis Blog the 2nd of October 2024, for
more info visit https://tillitis.se
2025-10-30 13:07:59 +01:00
Jonas Thörnblad
ab4ef5fdf9
fpga: Introduce CTS signals for UART
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Add incoming and outgoing CTS (Clear To Send) signals for the FPGA to
let the CH552 and FPGA signal each other that it is OK to send UART
data. The CTS signals indicate "OK to send" if high. If an incoming
CTS signal goes low, the receiver of that signal should immediatly
stop sending UART data.
2025-02-11 13:50:04 +01:00
Jonas Thörnblad
ede92af2c1
Updated application_fpga_verilator.cc to match module application_fpga_sim.
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- include printout of used clock and baud rate speed
- Use the the same clock frequency as target
2024-11-28 16:10:01 +01:00
Daniel Lublin
675fa1087f
Raise bps to 62500
2022-10-21 14:10:41 +02:00
Daniel Lublin
2bb62af183
Update bit divisor calc in verilator's uart to our current 18 MHz
2022-10-03 13:11:53 +02:00
Daniel Lublin
10b7951933
Let verilator print when touched by kill -USR1
2022-09-21 11:25:13 +02:00
Joachim Strömbergson
715de60f4a
Make initial public release
2022-09-19 08:51:11 +02:00
