App is embedded in firmware and is loaded into app RAM when firmware
starts.
App continuously calls SET_LED syscalls.
Simulation: `make tb_application_fpga_irqpoc_c_example`
Allow FW RAM access only in the following execution contexts:
- Firmware mode
- IRQ_SYSCALL_HI
Input port `system_mode` of the `fw_ram` module is replaced with an
enable port. Since access to FW RAM not longer depend only on
system_mode
Adds a basic example firmware that copies an app to app RAM. The app
triggers syscall interrupts and tries to execute ROM code from app mode.
A make target (`tb_application_fpga_irqpoc_with_app`) that simulates a
Tkey running the firmware is added.
A proof-of-concept of enabling PicoRV32 interrupts. Two interrupt
sources, which can be triggered by writes to memory addresses, are
added. The design has only been simulated, not run on hardware.
Synthesis:
Ice40 LC utilization is 93% (4934/5280) when built using tkey-builder:4
Simulation:
A `tb_application_fpga_irqpoc` target is added. Running `make
tb_application_fpga_irqpoc` creates `tb_application_fpga_sim.fst` which
can be inspected in GTKWave or Surfer.
Firmware:
A simple firmware is added in `fw/irqpoc`. It enables both interrupts
and triggers each interrupt once.
Custom PicoRV32 instructions are located in `custom_ops.S`. It is
imported from upstream PicoRV32 commit:
70f3c33ac8
Add incoming and outgoing CTS (Clear To Send) signals for the FPGA to
let the CH552 and FPGA signal each other that it is OK to send UART
data. The CTS signals indicate "OK to send" if high. If an incoming
CTS signal goes low, the receiver of that signal should immediatly
stop sending UART data.
