Commit Graph

18 Commits

Author SHA1 Message Date
Daniel Lublin
3435941eab
Remove version suffixes, no longer needed on ubuntu 22.10 (clang 15)
Signed-off-by: Daniel Lublin <daniel@lublin.se>
2022-11-23 09:47:48 +01:00
Daniel Lublin
4b4f014d38
Rename to TK1 2022-10-26 09:20:02 +02:00
Michael Cardell Widerkrantz
b8f1d4a083
Add make target secret, update quickstart 2022-10-20 17:02:56 +02:00
Joachim Strömbergson
51a22dc32c Merge branch 'fw_ram' 2022-10-13 13:16:53 +02:00
Joachim Strömbergson
b37b377a7e
Change optimization to Os since we want compact code 2022-10-13 09:26:49 +02:00
Joachim Strömbergson
192ce47fce
Fix #18 with incorrect clock frequency in analysis 2022-10-12 10:25:37 +02:00
Daniel Lublin
200ef26f36
Correct 2022-10-11 20:46:21 +02:00
Daniel Lublin
4d927ce426
Fix size_mismatch for testfw 2022-10-11 17:25:19 +02:00
Daniel Lublin
96746b2de0
Clarify BRAM_FW_SIZE 2022-10-11 17:25:00 +02:00
Joachim Strömbergson
a51619e5b7
Add fw_ram module 2022-10-11 16:58:26 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG 2022-10-11 13:17:04 +02:00
Joachim Strömbergson
5087a67376
Reduce FW ROM size to 6 kByte 2022-10-11 12:54:44 +02:00
Michael Cardell Widerkrantz
df7a26c28c
Compile firmware with -DNOCONSOLE 2022-10-07 11:19:53 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following:
Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
2022-10-06 13:23:30 +02:00
Joachim Strömbergson
b2ca3f2ea0
Fix Verilator sim by adding separate reset generator 2022-10-03 12:55:24 +02:00
Joachim Strömbergson
90a57c4948
Use PLL and global buffer to increas clock speed 2022-09-27 16:41:38 +02:00
Daniel Lublin
40803993e1
Make synth.json depend on data/{uds,udi}.hex; revise docs 2022-09-20 16:37:04 +02:00
Joachim Strömbergson
715de60f4a Make initial public release 2022-09-19 08:51:11 +02:00