5 commits

Author	SHA1	Message	Date
Jonas Thörnblad	ede92af2c1	Updated application_fpga_verilator.cc to match module application_fpga_sim. ... - include printout of used clock and baud rate speed - Use the the same clock frequency as target	2024-11-28 16:10:01 +01:00
Daniel Lublin	675fa1087f	Raise bps to 62500	2022-10-21 14:10:41 +02:00
Daniel Lublin	2bb62af183	Update bit divisor calc in verilator's uart to our current 18 MHz	2022-10-03 13:11:53 +02:00
Daniel Lublin	10b7951933	Let verilator print when touched by kill -USR1	2022-09-21 11:25:13 +02:00
Joachim Strömbergson	715de60f4a	Make initial public release	2022-09-19 08:51:11 +02:00