2 commits

Author	SHA1	Message	Date
Mikael Ågren	1e20dba10a	fpga/ch552: Swap fpga_cts and ch552_cts pins ... The FPGA uwg30 package cannot use B3 as an input when an instance of SB_PLL40_CORE is placed. We swap fpga_cts and ch552_cts to make B3 (from here on fpga_cts) an output. For more info check out: FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf chapter "5.1 PLL Placement Rules"	2025-05-19 08:55:26 +02:00
Mikael Ågren	c98249c3e3	fpga: Experimental fpga build for uwg30 package ... nextpnr-ice40 fails with: ``` Info: Placing PLLs.. ERROR: PLL 'reset_gen_inst.pll_inst' couldn't be placed anywhere, no suitable BEL found. PLL bel 'X12/Y31/pll_3' cannot be used as it conflicts with input 'interface_ch552_cts$sb_io' on pin 'B3'. ```	2025-05-19 08:55:22 +02:00