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1e20dba10a
The FPGA uwg30 package cannot use B3 as an input when an instance of SB_PLL40_CORE is placed. We swap fpga_cts and ch552_cts to make B3 (from here on fpga_cts) an output. For more info check out: FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf chapter "5.1 PLL Placement Rules"
47 lines
1 KiB
Text
47 lines
1 KiB
Text
#=======================================================================
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#
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# application_fpga_tk1_uwg30.pcf
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# ------------------------------
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# Pin constraints file for the Application FPGA design to be used
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# on the tk1 board with the CH552 MCU used as a USB-serial chip.
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# This version targets the UWG30 package.
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#
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#
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# Copyright (C) 2022 - Tillitis AB
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#=======================================================================
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# UART.
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set_io interface_rx A2
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set_io interface_tx A1
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set_io interface_ch552_cts A4
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set_io interface_fpga_cts B3
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# SPI master to flash memory.
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set_io spi_miso E1
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set_io spi_sck D1
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set_io spi_ss C1
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set_io spi_mosi F1
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# Touch sense.
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set_io touch_event B1
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# GPIOs.
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#set_io app_gpio1 36
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#set_io app_gpio2 38
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#set_io app_gpio3 45
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#set_io app_gpio4 46
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# LEDs
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set_io led_r A5
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set_io led_b B5
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set_io led_g C5
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#=======================================================================
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# EOF application_fpga_tk1_uwg30.pcf
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#=======================================================================
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