The FPGA uwg30 package cannot use B3 as an input when an instance of
SB_PLL40_CORE is placed. We swap fpga_cts and ch552_cts to make B3 (from
here on fpga_cts) an output.
For more info check out:
FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf chapter "5.1
PLL Placement Rules"
nextpnr-ice40 fails with:
```
Info: Placing PLLs..
ERROR: PLL 'reset_gen_inst.pll_inst' couldn't be placed anywhere, no
suitable BEL found.
PLL bel 'X12/Y31/pll_3' cannot be used as it conflicts with input
'interface_ch552_cts$sb_io' on pin 'B3'.
```
Add incoming and outgoing CTS (Clear To Send) signals for the FPGA to
let the CH552 and FPGA signal each other that it is OK to send UART
data. The CTS signals indicate "OK to send" if high. If an incoming
CTS signal goes low, the receiver of that signal should immediatly
stop sending UART data.
- NOTE: This is an optional feature, not built by default. Not included
in the tk1 for sale at Tillitis shop.
- This makes it possible to interface the SPI flash onboard TKey.
- To include the SPI master in the build, use `make application_fpga.bin
YOSYS_FLAG=-DINCLUDE_SPI_MASTER`.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
