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Squashed commit of the following:

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Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
This commit is contained in:
Joachim Strömbergson 2022-10-06 13:23:30 +02:00
parent 2bb62af183
commit c35e7680ea
No known key found for this signature in database
GPG key ID: 865B8A548EA61679
15 changed files with 102 additions and 72 deletions
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4
hw/application_fpga/core/mta1/rtl/mta1.v
View file

@ -78,7 +78,7 @@ module mta1(
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] cdi_mem [0 : 7];
reg [31 : 0] cdi_mem_we;
reg cdi_mem_we;
reg [31 : 0] udi_mem [0 : 1];
initial $readmemh(`UDI_HEX, udi_mem);
@ -130,6 +130,7 @@ module mta1(
//----------------------------------------------------------------
// Module instance.
//----------------------------------------------------------------
/* verilator lint_off PINMISSING */
SB_RGBA_DRV #(
.CURRENT_MODE("0b1"), // half-current mode
.RGB0_CURRENT("0b000001"), // 2 mA
@ -145,6 +146,7 @@ module mta1(
.RGB2PWM(led_reg[LED_B_BIT]),
.CURREN(1'b1)
);
/* verilator lint_on PINMISSING */
//----------------------------------------------------------------

17
hw/application_fpga/core/picorv32/rtl/picorv32.v
View file

@ -178,8 +178,9 @@ module picorv32 #(
reg [31:0] next_insn_opcode;
reg [31:0] dbg_insn_opcode;
reg [31:0] dbg_insn_addr;
/* verilator lint_off UNUSED */
reg [31:0] dbg_insn_addr;
wire dbg_mem_valid = mem_valid;
wire dbg_mem_instr = mem_instr;
wire dbg_mem_ready = mem_ready;
@ -187,6 +188,7 @@ module picorv32 #(
wire [31:0] dbg_mem_wdata = mem_wdata;
wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
wire [31:0] dbg_mem_rdata = mem_rdata;
/* verilator lint_on UNUSED */
assign pcpi_rs1 = reg_op1;
assign pcpi_rs2 = reg_op2;
@ -372,7 +374,6 @@ module picorv32 #(
wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
@ -687,6 +688,8 @@ module picorv32 #(
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
reg [63:0] new_ascii_instr;
/* verilator lint_off UNUSED */
`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
`FORMAL_KEEP reg [31:0] dbg_insn_imm;
`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
@ -696,6 +699,7 @@ module picorv32 #(
`FORMAL_KEEP reg [31:0] dbg_rs2val;
`FORMAL_KEEP reg dbg_rs1val_valid;
`FORMAL_KEEP reg dbg_rs2val_valid;
/* verilator lint_on UNUSED */
always @* begin
new_ascii_instr = " ";
@ -764,7 +768,10 @@ module picorv32 #(
reg dbg_next;
wire launch_next_insn;
/* verilator lint_off UNUSED */
reg dbg_valid_insn;
/* verilator lint_on UNUSED */
reg [63:0] cached_ascii_instr;
reg [31:0] cached_insn_imm;
@ -1176,7 +1183,9 @@ module picorv32 #(
reg [7:0] cpu_state;
reg [1:0] irq_state;
/* verilator lint_off UNUSED */
`FORMAL_KEEP reg [127:0] dbg_ascii_state;
/* verilator lint_on UNUSED */
always @* begin
dbg_ascii_state = "";
@ -2318,7 +2327,9 @@ module picorv32_pcpi_fast_mul #(
input clk, resetn,
input pcpi_valid,
/* verilator lint_off UNUSED */
input [31:0] pcpi_insn,
/* verilator lint_on UNUSED */
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output pcpi_wr,
@ -2416,7 +2427,9 @@ module picorv32_pcpi_div (
input clk, resetn,
input pcpi_valid,
/* verilator lint_off UNUSED */
input [31:0] pcpi_insn,
/* verilator lint_on UNUSED */
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,

6
hw/application_fpga/core/touch_sense/rtl/touch_sense.v
View file

@ -67,9 +67,9 @@ module touch_sense(
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg [31 : 0] tmp_ready;
reg api_clear_event;
reg [31 : 0] tmp_read_data;
reg tmp_ready;
reg api_clear_event;
//----------------------------------------------------------------

2
hw/application_fpga/core/trng/rtl/figaro.v
View file

@ -20,7 +20,9 @@ module figaro(
input wire cs,
input wire we,
input wire [7 : 0] address,
/* verilator lint_off UNUSED */
input wire [31 : 0] write_data,
/* verilator lint_on UNUSED */
output wire [31 : 0] read_data,
output wire ready
);

23
hw/application_fpga/core/trng/rtl/firo.v
View file

@ -26,23 +26,26 @@ module firo(
// Registers and wires.
//----------------------------------------------------------------
reg entropy_reg;
/* verilator lint_off UNOPTFLAT */
wire [10 : 0] f;
/* verilator lint_on UNOPTFLAT */
//---------------------------------------------------------------
// Combinational loop inverters.
//---------------------------------------------------------------
/* verilator lint_off PINMISSING */
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv1 (.I0(f[0]), .O(f[1]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv2 (.I0(f[1]), .O(f[2]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv3 (.I0(f[2]), .O(f[3]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv4 (.I0(f[3]), .O(f[4]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv5 (.I0(f[4]), .O(f[5]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv6 (.I0(f[5]), .O(f[6]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv7 (.I0(f[6]), .O(f[7]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv8 (.I0(f[7]), .O(f[8]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv9 (.I0(f[8]), .O(f[9]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv10 (.I0(f[9]), .O(f[10]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv1 (.I0(f[0]), .O(f[1]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv2 (.I0(f[1]), .O(f[2]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv3 (.I0(f[2]), .O(f[3]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv4 (.I0(f[3]), .O(f[4]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv5 (.I0(f[4]), .O(f[5]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv6 (.I0(f[5]), .O(f[6]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv7 (.I0(f[6]), .O(f[7]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv8 (.I0(f[7]), .O(f[8]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv9 (.I0(f[8]), .O(f[9]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv10 (.I0(f[9]), .O(f[10]));
/* verilator lint_on PINMISSING */

27
hw/application_fpga/core/trng/rtl/garo.v
View file

@ -26,26 +26,29 @@ module garo(
// Registers and wires.
//----------------------------------------------------------------
reg entropy_reg;
/* verilator lint_off UNOPTFLAT */
wire [11 : 0] g;
wire [11 : 0] gp;
/* verilator lint_on UNOPTFLAT */
//---------------------------------------------------------------
// Combinational loop inverters.
//---------------------------------------------------------------
/* verilator lint_off PINMISSING */
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv1 (.I0(g[0]), .O(gp[0]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv2 (.I0(g[1]), .O(gp[1]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv3 (.I0(g[2]), .O(gp[2]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv4 (.I0(g[3]), .O(gp[3]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv5 (.I0(g[4]), .O(gp[4]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv6 (.I0(g[5]), .O(gp[5]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv7 (.I0(g[6]), .O(gp[6]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv8 (.I0(g[7]), .O(gp[7]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv9 (.I0(g[8]), .O(gp[8]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv10 (.I0(g[9]), .O(gp[9]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv11 (.I0(g[10]), .O(gp[10]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv12 (.I0(g[11]), .O(gp[11]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv1 (.I0(g[0]), .O(gp[0]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv2 (.I0(g[1]), .O(gp[1]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv3 (.I0(g[2]), .O(gp[2]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv4 (.I0(g[3]), .O(gp[3]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv5 (.I0(g[4]), .O(gp[4]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv6 (.I0(g[5]), .O(gp[5]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv7 (.I0(g[6]), .O(gp[6]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv8 (.I0(g[7]), .O(gp[7]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv9 (.I0(g[8]), .O(gp[8]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv10 (.I0(g[9]), .O(gp[9]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv11 (.I0(g[10]), .O(gp[10]));
(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv12 (.I0(g[11]), .O(gp[11]));
/* verilator lint_on PINMISSING */

2
hw/application_fpga/core/uart/rtl/uart.v
View file

@ -58,7 +58,9 @@ module uart(
input wire cs,
input wire we,
input wire [7 : 0] address,
/* verilator lint_off UNUSED */
input wire [31 : 0] write_data,
/* verilator lint_on UNUSED */
output wire [31 : 0] read_data,
output wire ready
);

26
hw/application_fpga/core/uart/rtl/uart_core.v
View file

@ -17,7 +17,7 @@
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
//
//
// SPDX-License-Identifier: BSD-2-Clause
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
@ -96,8 +96,8 @@ module uart_core(
reg [7 : 0] rxd_byte_reg;
reg rxd_byte_we;
reg [4 : 0] rxd_bit_ctr_reg;
reg [4 : 0] rxd_bit_ctr_new;
reg [3 : 0] rxd_bit_ctr_reg;
reg [3 : 0] rxd_bit_ctr_new;
reg rxd_bit_ctr_we;
reg rxd_bit_ctr_rst;
reg rxd_bit_ctr_inc;
@ -124,8 +124,8 @@ module uart_core(
reg [7 : 0] txd_byte_new;
reg txd_byte_we;
reg [4 : 0] txd_bit_ctr_reg;
reg [4 : 0] txd_bit_ctr_new;
reg [3 : 0] txd_bit_ctr_reg;
reg [3 : 0] txd_bit_ctr_new;
reg txd_bit_ctr_we;
reg txd_bit_ctr_rst;
reg txd_bit_ctr_inc;
@ -175,14 +175,14 @@ module uart_core(
rxd0_reg <= 1'b0;
rxd_reg <= 1'b0;
rxd_byte_reg <= 8'h0;
rxd_bit_ctr_reg <= 5'h0;
rxd_bit_ctr_reg <= 4'h0;
rxd_bitrate_ctr_reg <= 16'h0;
rxd_syn_reg <= 0;
erx_ctrl_reg <= ERX_IDLE;
txd_reg <= 1'b1;
txd_byte_reg <= 8'h0;
txd_bit_ctr_reg <= 5'h0;
txd_bit_ctr_reg <= 4'h0;
txd_bitrate_ctr_reg <= 16'h0;
txd_ready_reg <= 1'b1;
etx_ctrl_reg <= ETX_IDLE;
@ -247,11 +247,11 @@ module uart_core(
//----------------------------------------------------------------
always @*
begin: rxd_bit_ctr
rxd_bit_ctr_new = 5'h0;
rxd_bit_ctr_new = 4'h0;
rxd_bit_ctr_we = 1'b0;
if (rxd_bit_ctr_rst) begin
rxd_bit_ctr_new = 5'h0;
rxd_bit_ctr_new = 4'h0;
rxd_bit_ctr_we = 1'b1;
end
@ -294,11 +294,11 @@ module uart_core(
//----------------------------------------------------------------
always @*
begin: txd_bit_ctr
txd_bit_ctr_new = 5'h0;
txd_bit_ctr_new = 4'h0;
txd_bit_ctr_we = 1'h0;
if (txd_bit_ctr_rst) begin
txd_bit_ctr_new = 5'h0;
txd_bit_ctr_new = 4'h0;
txd_bit_ctr_we = 1'h1;
end
@ -391,7 +391,7 @@ module uart_core(
rxd_byte_we = 1;
rxd_bit_ctr_inc = 1;
rxd_bitrate_ctr_rst = 1;
if (rxd_bit_ctr_reg == data_bits - 1) begin
if (rxd_bit_ctr_reg == (data_bits - 1)) begin
erx_ctrl_new = ERX_STOP;
erx_ctrl_we = 1;
end
@ -501,7 +501,7 @@ module uart_core(
end
else begin
txd_new = txd_byte_reg[txd_bit_ctr_reg];
txd_new = txd_byte_reg[txd_bit_ctr_reg[2 : 0]];
txd_we = 1;
txd_bit_ctr_inc = 1;
end

2
hw/application_fpga/core/uart/rtl/uart_fifo.v
View file

@ -57,12 +57,10 @@ module uart_fifo(
reg [7: 0] in_ptr_reg;
reg [7: 0] in_ptr_new;
reg in_ptr_inc;
reg in_ptr_we;
reg [7: 0] out_ptr_reg;
reg [7: 0] out_ptr_new;
reg out_ptr_inc;
reg out_ptr_we;
reg [7: 0] byte_ctr_reg;

2
hw/application_fpga/core/uds/rtl/uds.v
View file

@ -17,7 +17,7 @@ module uds(
input wire clk,
input wire reset_n,
output wire fw_app_mode,
input wire fw_app_mode,
input wire cs,
input wire [7 : 0] address,