diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile
index ceddf44..62de92e 100644
--- a/hw/application_fpga/Makefile
+++ b/hw/application_fpga/Makefile
@@ -146,7 +146,7 @@ lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
 	-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
 	-DUDS_HEX=\"$(P)/data/uds.hex\" \
 	-DUDI_HEX=\"$(P)/data/udi.hex\" \
-	--top-module application_fpga $^
+	--top-module application_fpga $^ &> lint_issues.txt
 .PHONY: lint
 
 
@@ -257,6 +257,7 @@ clean: clean_fw
 	rm -f synth.{log,v,json} route.v application_fpga.{asc,bin,vcd} application_fpga_testfw.bin
 	rm -f tb_application_fpga.vvp synth_tb.vvp route_tb.vvp
 	rm -f *.vcd
+	rm -f lint_issues.txt
 	rm -rf verilated
 	rm -f tools/tpt/*.hex
 	rm -rf tools/tpt/__pycache__
diff --git a/hw/application_fpga/core/mta1/rtl/mta1.v b/hw/application_fpga/core/mta1/rtl/mta1.v
index 052ea34..55167c9 100644
--- a/hw/application_fpga/core/mta1/rtl/mta1.v
+++ b/hw/application_fpga/core/mta1/rtl/mta1.v
@@ -78,7 +78,7 @@ module mta1(
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
   reg [31 : 0] cdi_mem [0 : 7];
-  reg [31 : 0] cdi_mem_we;
+  reg          cdi_mem_we;
 
   reg [31 : 0] udi_mem [0 : 1];
   initial $readmemh(`UDI_HEX, udi_mem);
@@ -130,6 +130,7 @@ module mta1(
   //----------------------------------------------------------------
   // Module instance.
   //----------------------------------------------------------------
+  /* verilator lint_off PINMISSING */
   SB_RGBA_DRV #(
                 .CURRENT_MODE("0b1"),       // half-current mode
                 .RGB0_CURRENT("0b000001"),  // 2 mA
@@ -145,6 +146,7 @@ module mta1(
                             .RGB2PWM(led_reg[LED_B_BIT]),
                             .CURREN(1'b1)
     );
+  /* verilator lint_on PINMISSING */
 
 
   //----------------------------------------------------------------
diff --git a/hw/application_fpga/core/picorv32/rtl/picorv32.v b/hw/application_fpga/core/picorv32/rtl/picorv32.v
index c55e2ac..bb1872e 100644
--- a/hw/application_fpga/core/picorv32/rtl/picorv32.v
+++ b/hw/application_fpga/core/picorv32/rtl/picorv32.v
@@ -178,8 +178,9 @@ module picorv32 #(
 
 	reg [31:0] next_insn_opcode;
 	reg [31:0] dbg_insn_opcode;
-	reg [31:0] dbg_insn_addr;
 
+  /* verilator lint_off UNUSED */
+	reg [31:0] dbg_insn_addr;
 	wire dbg_mem_valid = mem_valid;
 	wire dbg_mem_instr = mem_instr;
 	wire dbg_mem_ready = mem_ready;
@@ -187,6 +188,7 @@ module picorv32 #(
 	wire [31:0] dbg_mem_wdata = mem_wdata;
 	wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
 	wire [31:0] dbg_mem_rdata = mem_rdata;
+  /* verilator lint_on UNUSED */
 
 	assign pcpi_rs1 = reg_op1;
 	assign pcpi_rs2 = reg_op2;
@@ -372,7 +374,6 @@ module picorv32 #(
 	wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
 	assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
 
-	wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
 	wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
 			(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
 
@@ -687,6 +688,8 @@ module picorv32 #(
 	assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
 
 	reg [63:0] new_ascii_instr;
+
+  /* verilator lint_off UNUSED */
 	`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
 	`FORMAL_KEEP reg [31:0] dbg_insn_imm;
 	`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
@@ -696,6 +699,7 @@ module picorv32 #(
 	`FORMAL_KEEP reg [31:0] dbg_rs2val;
 	`FORMAL_KEEP reg dbg_rs1val_valid;
 	`FORMAL_KEEP reg dbg_rs2val_valid;
+  /* verilator lint_on UNUSED */
 
 	always @* begin
 		new_ascii_instr = " ";
@@ -764,7 +768,10 @@ module picorv32 #(
 	reg dbg_next;
 
 	wire launch_next_insn;
+
+  /* verilator lint_off UNUSED */
 	reg dbg_valid_insn;
+  /* verilator lint_on UNUSED */
 
 	reg [63:0] cached_ascii_instr;
 	reg [31:0] cached_insn_imm;
@@ -1176,7 +1183,9 @@ module picorv32 #(
 	reg [7:0] cpu_state;
 	reg [1:0] irq_state;
 
+  /* verilator lint_off UNUSED */
 	`FORMAL_KEEP reg [127:0] dbg_ascii_state;
+  /* verilator lint_on UNUSED */
 
 	always @* begin
 		dbg_ascii_state = "";
@@ -2318,7 +2327,9 @@ module picorv32_pcpi_fast_mul #(
 	input clk, resetn,
 
 	input             pcpi_valid,
+  /* verilator lint_off UNUSED */
 	input      [31:0] pcpi_insn,
+  /* verilator lint_on UNUSED */
 	input      [31:0] pcpi_rs1,
 	input      [31:0] pcpi_rs2,
 	output            pcpi_wr,
@@ -2416,7 +2427,9 @@ module picorv32_pcpi_div (
 	input clk, resetn,
 
 	input             pcpi_valid,
+  /* verilator lint_off UNUSED */
 	input      [31:0] pcpi_insn,
+  /* verilator lint_on UNUSED */
 	input      [31:0] pcpi_rs1,
 	input      [31:0] pcpi_rs2,
 	output reg        pcpi_wr,
diff --git a/hw/application_fpga/core/touch_sense/rtl/touch_sense.v b/hw/application_fpga/core/touch_sense/rtl/touch_sense.v
index a193583..754c857 100644
--- a/hw/application_fpga/core/touch_sense/rtl/touch_sense.v
+++ b/hw/application_fpga/core/touch_sense/rtl/touch_sense.v
@@ -67,9 +67,9 @@ module touch_sense(
   //----------------------------------------------------------------
   // Wires.
   //----------------------------------------------------------------
-  reg [31 : 0]   tmp_read_data;
-  reg [31 : 0]   tmp_ready;
-  reg            api_clear_event;
+  reg [31 : 0] tmp_read_data;
+  reg          tmp_ready;
+  reg          api_clear_event;
 
 
   //----------------------------------------------------------------
diff --git a/hw/application_fpga/core/trng/rtl/figaro.v b/hw/application_fpga/core/trng/rtl/figaro.v
index 806e04d..9e28707 100644
--- a/hw/application_fpga/core/trng/rtl/figaro.v
+++ b/hw/application_fpga/core/trng/rtl/figaro.v
@@ -20,7 +20,9 @@ module figaro(
               input wire           cs,
               input wire           we,
               input wire  [7 : 0]  address,
+  /* verilator lint_off UNUSED */
               input wire  [31 : 0] write_data,
+  /* verilator lint_on UNUSED */
               output wire [31 : 0] read_data,
 	      output wire          ready
              );
diff --git a/hw/application_fpga/core/trng/rtl/firo.v b/hw/application_fpga/core/trng/rtl/firo.v
index c001033..5125c02 100644
--- a/hw/application_fpga/core/trng/rtl/firo.v
+++ b/hw/application_fpga/core/trng/rtl/firo.v
@@ -26,23 +26,26 @@ module firo(
   // Registers and wires.
   //----------------------------------------------------------------
   reg entropy_reg;
+
+  /* verilator lint_off UNOPTFLAT */
   wire [10 : 0] f;
+  /* verilator lint_on UNOPTFLAT */
 
 
   //---------------------------------------------------------------
   // Combinational loop inverters.
   //---------------------------------------------------------------
   /* verilator lint_off PINMISSING */
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv1  (.I0(f[0]), .O(f[1]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv2  (.I0(f[1]), .O(f[2]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv3  (.I0(f[2]), .O(f[3]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv4  (.I0(f[3]), .O(f[4]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv5  (.I0(f[4]), .O(f[5]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv6  (.I0(f[5]), .O(f[6]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv7  (.I0(f[6]), .O(f[7]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv8  (.I0(f[7]), .O(f[8]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv9  (.I0(f[8]), .O(f[9]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv10 (.I0(f[9]), .O(f[10]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv1  (.I0(f[0]), .O(f[1]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv2  (.I0(f[1]), .O(f[2]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv3  (.I0(f[2]), .O(f[3]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv4  (.I0(f[3]), .O(f[4]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv5  (.I0(f[4]), .O(f[5]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv6  (.I0(f[5]), .O(f[6]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv7  (.I0(f[6]), .O(f[7]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv8  (.I0(f[7]), .O(f[8]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv9  (.I0(f[8]), .O(f[9]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv10 (.I0(f[9]), .O(f[10]));
   /* verilator lint_on PINMISSING */
 
 
diff --git a/hw/application_fpga/core/trng/rtl/garo.v b/hw/application_fpga/core/trng/rtl/garo.v
index 4bca855..74808fe 100644
--- a/hw/application_fpga/core/trng/rtl/garo.v
+++ b/hw/application_fpga/core/trng/rtl/garo.v
@@ -26,26 +26,29 @@ module garo(
   // Registers and wires.
   //----------------------------------------------------------------
   reg entropy_reg;
+
+  /* verilator lint_off UNOPTFLAT */
   wire [11 : 0] g;
   wire [11 : 0] gp;
+  /* verilator lint_on UNOPTFLAT */
 
 
   //---------------------------------------------------------------
   // Combinational loop inverters.
   //---------------------------------------------------------------
   /* verilator lint_off PINMISSING */
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv1  (.I0(g[0]),  .O(gp[0]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv2  (.I0(g[1]),  .O(gp[1]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv3  (.I0(g[2]),  .O(gp[2]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv4  (.I0(g[3]),  .O(gp[3]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv5  (.I0(g[4]),  .O(gp[4]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv6  (.I0(g[5]),  .O(gp[5]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv7  (.I0(g[6]),  .O(gp[6]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv8  (.I0(g[7]),  .O(gp[7]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv9  (.I0(g[8]),  .O(gp[8]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv10 (.I0(g[9]),  .O(gp[9]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv11 (.I0(g[10]), .O(gp[10]));
-  (* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv12 (.I0(g[11]), .O(gp[11]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv1  (.I0(g[0]),  .O(gp[0]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv2  (.I0(g[1]),  .O(gp[1]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv3  (.I0(g[2]),  .O(gp[2]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv4  (.I0(g[3]),  .O(gp[3]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv5  (.I0(g[4]),  .O(gp[4]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv6  (.I0(g[5]),  .O(gp[5]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv7  (.I0(g[6]),  .O(gp[6]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv8  (.I0(g[7]),  .O(gp[7]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv9  (.I0(g[8]),  .O(gp[8]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv10 (.I0(g[9]),  .O(gp[9]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv11 (.I0(g[10]), .O(gp[10]));
+  (* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv12 (.I0(g[11]), .O(gp[11]));
   /* verilator lint_on PINMISSING */
 
 
diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v
index 729418d..b31ecd8 100644
--- a/hw/application_fpga/core/uart/rtl/uart.v
+++ b/hw/application_fpga/core/uart/rtl/uart.v
@@ -58,7 +58,9 @@ module uart(
             input wire           cs,
             input wire           we,
             input wire [7 : 0]   address,
+  /* verilator lint_off UNUSED */
             input wire [31 : 0]  write_data,
+  /* verilator lint_on UNUSED */
             output wire [31 : 0] read_data,
             output wire          ready
            );
diff --git a/hw/application_fpga/core/uart/rtl/uart_core.v b/hw/application_fpga/core/uart/rtl/uart_core.v
index 9a92ee4..59c3471 100644
--- a/hw/application_fpga/core/uart/rtl/uart_core.v
+++ b/hw/application_fpga/core/uart/rtl/uart_core.v
@@ -17,7 +17,7 @@
 //
 // Author: Joachim Strombergson
 // Copyright (c) 2014, Secworks Sweden AB
-// 
+//
 // SPDX-License-Identifier: BSD-2-Clause
 // Redistribution and use in source and binary forms, with or
 // without modification, are permitted provided that the following
@@ -96,8 +96,8 @@ module uart_core(
   reg [7 : 0]  rxd_byte_reg;
   reg          rxd_byte_we;
 
-  reg [4 : 0]  rxd_bit_ctr_reg;
-  reg [4 : 0]  rxd_bit_ctr_new;
+  reg [3 : 0]  rxd_bit_ctr_reg;
+  reg [3 : 0]  rxd_bit_ctr_new;
   reg          rxd_bit_ctr_we;
   reg          rxd_bit_ctr_rst;
   reg          rxd_bit_ctr_inc;
@@ -124,8 +124,8 @@ module uart_core(
   reg [7 : 0]  txd_byte_new;
   reg          txd_byte_we;
 
-  reg [4 : 0]  txd_bit_ctr_reg;
-  reg [4 : 0]  txd_bit_ctr_new;
+  reg [3 : 0]  txd_bit_ctr_reg;
+  reg [3 : 0]  txd_bit_ctr_new;
   reg          txd_bit_ctr_we;
   reg          txd_bit_ctr_rst;
   reg          txd_bit_ctr_inc;
@@ -175,14 +175,14 @@ module uart_core(
         rxd0_reg            <= 1'b0;
         rxd_reg             <= 1'b0;
         rxd_byte_reg        <= 8'h0;
-        rxd_bit_ctr_reg     <= 5'h0;
+        rxd_bit_ctr_reg     <= 4'h0;
         rxd_bitrate_ctr_reg <= 16'h0;
         rxd_syn_reg         <= 0;
         erx_ctrl_reg        <= ERX_IDLE;
 
         txd_reg             <= 1'b1;
         txd_byte_reg        <= 8'h0;
-        txd_bit_ctr_reg     <= 5'h0;
+        txd_bit_ctr_reg     <= 4'h0;
         txd_bitrate_ctr_reg <= 16'h0;
         txd_ready_reg       <= 1'b1;
         etx_ctrl_reg        <= ETX_IDLE;
@@ -247,11 +247,11 @@ module uart_core(
   //----------------------------------------------------------------
   always @*
     begin: rxd_bit_ctr
-      rxd_bit_ctr_new = 5'h0;
+      rxd_bit_ctr_new = 4'h0;
       rxd_bit_ctr_we  = 1'b0;
 
       if (rxd_bit_ctr_rst) begin
-        rxd_bit_ctr_new = 5'h0;
+        rxd_bit_ctr_new = 4'h0;
         rxd_bit_ctr_we  = 1'b1;
       end
 
@@ -294,11 +294,11 @@ module uart_core(
   //----------------------------------------------------------------
   always @*
     begin: txd_bit_ctr
-      txd_bit_ctr_new = 5'h0;
+      txd_bit_ctr_new = 4'h0;
       txd_bit_ctr_we  = 1'h0;
 
       if (txd_bit_ctr_rst) begin
-        txd_bit_ctr_new = 5'h0;
+        txd_bit_ctr_new = 4'h0;
         txd_bit_ctr_we  = 1'h1;
       end
 
@@ -391,7 +391,7 @@ module uart_core(
             rxd_byte_we         = 1;
             rxd_bit_ctr_inc     = 1;
             rxd_bitrate_ctr_rst = 1;
-            if (rxd_bit_ctr_reg == data_bits - 1) begin
+            if (rxd_bit_ctr_reg == (data_bits - 1)) begin
               erx_ctrl_new = ERX_STOP;
               erx_ctrl_we  = 1;
             end
@@ -501,7 +501,7 @@ module uart_core(
             end
 
             else begin
-              txd_new         = txd_byte_reg[txd_bit_ctr_reg];
+              txd_new         = txd_byte_reg[txd_bit_ctr_reg[2 : 0]];
               txd_we          = 1;
               txd_bit_ctr_inc = 1;
             end
diff --git a/hw/application_fpga/core/uart/rtl/uart_fifo.v b/hw/application_fpga/core/uart/rtl/uart_fifo.v
index 02b7079..11fa3dd 100644
--- a/hw/application_fpga/core/uart/rtl/uart_fifo.v
+++ b/hw/application_fpga/core/uart/rtl/uart_fifo.v
@@ -57,12 +57,10 @@ module uart_fifo(
 
   reg [7: 0]   in_ptr_reg;
   reg [7: 0]   in_ptr_new;
-  reg          in_ptr_inc;
   reg          in_ptr_we;
 
   reg [7: 0]   out_ptr_reg;
   reg [7: 0]   out_ptr_new;
-  reg          out_ptr_inc;
   reg          out_ptr_we;
 
   reg [7: 0]   byte_ctr_reg;
diff --git a/hw/application_fpga/core/uds/rtl/uds.v b/hw/application_fpga/core/uds/rtl/uds.v
index 90350c9..8cff428 100644
--- a/hw/application_fpga/core/uds/rtl/uds.v
+++ b/hw/application_fpga/core/uds/rtl/uds.v
@@ -17,7 +17,7 @@ module uds(
            input wire           clk,
            input wire           reset_n,
 
-	   output wire          fw_app_mode,
+	   input wire           fw_app_mode,
 
            input wire           cs,
            input wire  [7 : 0]  address,
diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v
index ecef4ec..e95c442 100644
--- a/hw/application_fpga/rtl/application_fpga.v
+++ b/hw/application_fpga/rtl/application_fpga.v
@@ -69,7 +69,9 @@ module application_fpga(
 
   wire          cpu_valid;
   wire [03 : 0] cpu_wstrb;
+  /* verilator lint_off UNUSED */
   wire [31 : 0] cpu_addr;
+  /* verilator lint_on UNUSED */
   wire [31 : 0] cpu_wdata;
 
   /* verilator lint_off UNOPTFLAT */
@@ -195,9 +197,6 @@ module application_fpga(
 
 
   rom rom_inst(
-               .clk(clk),
-               .reset_n(reset_n),
-
                .cs(rom_cs),
                .address(rom_address),
                .read_data(rom_read_data),
@@ -353,29 +352,29 @@ module application_fpga(
 
       trng_cs             = 1'h0;
       trng_we             = |cpu_wstrb;
-      trng_address        = cpu_addr[10 : 2];
+      trng_address        = cpu_addr[9 : 2];
       trng_write_data     = cpu_wdata;
 
       timer_cs            = 1'h0;
       timer_we            = |cpu_wstrb;
-      timer_address       = cpu_addr[10 : 2];
+      timer_address       = cpu_addr[9 : 2];
       timer_write_data    = cpu_wdata;
 
       uds_cs              = 1'h0;
-      uds_address         = cpu_addr[10 : 2];
+      uds_address         = cpu_addr[9 : 2];
 
       uart_cs             = 1'h0;
       uart_we             = |cpu_wstrb;
-      uart_address        = cpu_addr[10 : 2];
+      uart_address        = cpu_addr[9 : 2];
       uart_write_data     = cpu_wdata;
 
       touch_sense_cs      = 1'h0;
       touch_sense_we      = |cpu_wstrb;
-      touch_sense_address = cpu_addr[10 : 2];
+      touch_sense_address = cpu_addr[9 : 2];
 
       mta1_cs             = 1'h0;
       mta1_we             = |cpu_wstrb;
-      mta1_address        = cpu_addr[10 : 2];
+      mta1_address        = cpu_addr[9 : 2];
       mta1_write_data     = cpu_wdata;
 
       if (cpu_valid && !muxed_ready_reg) begin
diff --git a/hw/application_fpga/rtl/clk_reset_gen.v b/hw/application_fpga/rtl/clk_reset_gen.v
index b8a1144..f0d20b3 100644
--- a/hw/application_fpga/rtl/clk_reset_gen.v
+++ b/hw/application_fpga/rtl/clk_reset_gen.v
@@ -46,36 +46,38 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
   //----------------------------------------------------------------
   // Core instantiations.
   //----------------------------------------------------------------
+  /* verilator lint_off PINMISSING */
+
   // Use the FPGA internal High Frequency OSCillator as clock source.
   // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
-  /* verilator lint_off PINMISSING */
   SB_HFOSC #(.CLKHF_DIV("0b10")
-	     ) u_hfosc (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
-  /* verilator lint_on PINMISSING */
+	     ) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
 
 
-  // PLL to generate a new clock frequency based on the HFOSC clock.
-  /* verilator lint_off PINMISSING */
+  // Use a PLL to generate a new clock frequency based on the HFOSC clock.
   SB_PLL40_CORE #(
 		  .FEEDBACK_PATH("SIMPLE"),
 		  .DIVR(4'b0000),	// DIVR =  0
 		  .DIVF(7'b0101111),	// DIVF = 47
 		  .DIVQ(3'b101),	// DIVQ =  5
 		  .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
-		  ) uut (
+		  ) pll_inst (
 			 .RESETB(1'b1),
 			 .BYPASS(1'b0),
 			 .REFERENCECLK(hfosc_clk),
 			 .PLLOUTCORE(pll_clk)
 			 );
-  /* verilator lint_on PINMISSING */
 
-  // Use a global buffer to distribute the clock.
-  SB_GB SB_GB_i (
+
+  // Use a Global Buffer to distribute the clock.
+  SB_GB gb_inst (
 		 .USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
 		 .GLOBAL_BUFFER_OUTPUT (clk)
 		 );
 
+  /* verilator lint_on PINMISSING */
+
+
   //----------------------------------------------------------------
   // reg_update.
   //----------------------------------------------------------------
diff --git a/hw/application_fpga/rtl/rom.v b/hw/application_fpga/rtl/rom.v
index da3c359..ee79347 100644
--- a/hw/application_fpga/rtl/rom.v
+++ b/hw/application_fpga/rtl/rom.v
@@ -15,11 +15,10 @@
 `default_nettype none
 
 module rom(
-	   input wire           clk,
-	   input wire           reset_n,
-
 	   input wire           cs,
+  /* verilator lint_off UNUSED */
 	   input wire  [11 : 0] address,
+  /* verilator lint_on UNUSED */
 	   output wire [31 : 0] read_data,
 	   output wire          ready
            );
@@ -35,6 +34,9 @@ module rom(
   // each pair store 256 32bit words.
   // The size of the EBR allocated to memory must match the
   // size of the firmware file generated by the Makefile.
+  //
+  // Max size for the ROM is 3072 words, and the address is
+  // 12 bits to support ROM with this number of words.
   localparam EBR_MEM_SIZE = `BRAM_FW_SIZE;
   reg [31 : 0] memory [0 : (EBR_MEM_SIZE - 1)];
   initial $readmemh(`FIRMWARE_HEX, memory);
@@ -56,7 +58,10 @@ module rom(
   //----------------------------------------------------------------
   always @*
     begin : rom_logic
+
+      /* verilator lint_off WIDTH */
       rom_rdata = memory[address];
+      /* verilator lint_on WIDTH */
       rom_ready = cs;
     end
 
diff --git a/hw/application_fpga/tb/application_fpga_vsim.v b/hw/application_fpga/tb/application_fpga_vsim.v
index 07739e1..f17fa67 100644
--- a/hw/application_fpga/tb/application_fpga_vsim.v
+++ b/hw/application_fpga/tb/application_fpga_vsim.v
@@ -366,29 +366,29 @@ module application_fpga(
 
       trng_cs             = 1'h0;
       trng_we             = |cpu_wstrb;
-      trng_address        = cpu_addr[10 : 2];
+      trng_address        = cpu_addr[9 : 2];
       trng_write_data     = cpu_wdata;
 
       timer_cs            = 1'h0;
       timer_we            = |cpu_wstrb;
-      timer_address       = cpu_addr[10 : 2];
+      timer_address       = cpu_addr[9 : 2];
       timer_write_data    = cpu_wdata;
 
       uds_cs              = 1'h0;
-      uds_address         = cpu_addr[10 : 2];
+      uds_address         = cpu_addr[9 : 2];
 
       uart_cs             = 1'h0;
       uart_we             = |cpu_wstrb;
-      uart_address        = cpu_addr[10 : 2];
+      uart_address        = cpu_addr[9 : 2];
       uart_write_data     = cpu_wdata;
 
       touch_sense_cs      = 1'h0;
       touch_sense_we      = |cpu_wstrb;
-      touch_sense_address = cpu_addr[10 : 2];
+      touch_sense_address = cpu_addr[9 : 2];
 
       mta1_cs             = 1'h0;
       mta1_we             = |cpu_wstrb;
-      mta1_address        = cpu_addr[10 : 2];
+      mta1_address        = cpu_addr[9 : 2];
       mta1_write_data     = cpu_wdata;
 
       if (cpu_valid && !muxed_ready_reg) begin