mirror of
https://github.com/tillitis/tillitis-key1.git
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c35e7680ea
Silence lint on intentional combinatinal loops Use better instance names, and a single lint pragma for all macros Remove unused pointer update signals Silence lint on wires where not all bits are used Change fw_app_mode to be an input port to allow access control Remove redundant, unused wire mem_busy Add lint pragma to ignore debug register only enabled by a define Remove clk and reset_n ports from the ROM Adding note and lint pragma for rom address width Fix incorrect register widths in uart_core Assign all 16 bits in LUT config Silence lint warnings on macro instances Correct bit extraction for core addresses to be eight bits wide Correct the bit width of cdi_mem_we wire Add specific output file for logging lint issues Correct bit width of tmp_ready to match one bit ready port
132 lines
3.7 KiB
Verilog
132 lines
3.7 KiB
Verilog
//======================================================================
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//
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// figaro.v
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// --------
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// Top level wrapper for the figaro core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module figaro(
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input wire clk,
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input wire reset_n,
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input wire cs,
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input wire we,
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input wire [7 : 0] address,
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/* verilator lint_off UNUSED */
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input wire [31 : 0] write_data,
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/* verilator lint_on UNUSED */
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_STATUS = 8'h09;
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localparam STATUS_READY_BIT = 0;
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localparam ADDR_SAMPLE_RATE = 8'h10;
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localparam ADDR_ENTROPY = 8'h20;
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localparam CORE_NAME0 = 32'h66696761; // "figa"
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localparam CORE_NAME1 = 32'h726f2020; // "ro "
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localparam CORE_VERSION = 32'h00000001;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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reg core_read_entropy;
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reg core_set_sample_rate;
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wire [31 : 0] core_entropy;
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wire core_ready;
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reg [31 : 0] tmp_read_data;
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reg tmp_ready;
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign read_data = tmp_read_data;
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assign ready = tmp_ready;
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//----------------------------------------------------------------
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// core instantiation.
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//----------------------------------------------------------------
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figaro_core core(
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.clk(clk),
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.reset_n(reset_n),
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.read_entropy(core_read_entropy),
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.set_sample_rate(core_set_sample_rate),
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.sample_rate(write_data[23 : 0]),
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.entropy(core_entropy),
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.ready(core_ready)
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);
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//----------------------------------------------------------------
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// api
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//
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// The interface command decoding logic.
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//----------------------------------------------------------------
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always @*
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begin : api
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core_read_entropy = 1'h0;
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core_set_sample_rate = 1'h0;
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tmp_read_data = 32'h0;
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tmp_ready = 1'h0;
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if (cs) begin
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tmp_ready = 1'h1;
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if (we) begin
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if (address == ADDR_SAMPLE_RATE) begin
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core_set_sample_rate = 1'h1;
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end
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end
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else begin
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if (address == ADDR_NAME0) begin
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tmp_read_data = CORE_NAME0;
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end
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if (address == ADDR_NAME1) begin
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tmp_read_data = CORE_NAME1;
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end
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if (address == ADDR_VERSION) begin
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tmp_read_data = CORE_VERSION;
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end
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if (address == ADDR_STATUS) begin
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tmp_read_data = {31'h0, core_ready};
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end
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if (address == ADDR_ENTROPY) begin
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tmp_read_data = core_entropy;
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core_read_entropy = 1'h1;
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end
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end
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end
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end // api
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endmodule // figaro
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//======================================================================
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// EOF figaro.v
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//======================================================================
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