Jared Boone
f4fdc21c20
PCB: Remove series resistors.
...
Not sure they're of much benefit.
2017-06-19 16:31:54 -07:00
Jared Boone
d1517702b7
PCB: Remove H1 (fifth hole).
2017-06-19 16:31:54 -07:00
Jared Boone
492a704e91
PCB: Interim revision number/date.
2017-06-19 16:31:54 -07:00
Jared Boone
b3c21c3762
CPLD: Ask Quartus to use maximum number of processors.
2017-06-13 21:21:25 -07:00
Jared Boone
9a0fa128c0
CPLD: Clean up *.qws files.
2017-06-13 21:20:19 -07:00
Jared Boone
76c2cc77af
CPLD: Move around some .gitignores.
2017-06-01 15:20:16 -07:00
Jared Boone
797e63a590
CPLD: Use correct bitstream for updating hardware.
...
Determine hardware version and use one of two CPLD bitstream files.
2017-05-31 22:28:07 -07:00
Jared Boone
73d62367d1
CPLD: Makefiles for both hardware variants.
2017-05-31 21:05:47 -07:00
Jared Boone
7c715ed913
CPLD: HDL for 20170522 hardware variant.
2017-05-31 15:21:25 -07:00
Jared Boone
0fd52a7483
CPLD: Move HDL project to hardware revision-specific directory.
2017-05-31 11:50:59 -07:00
Jared Boone
2add96d42d
CPLD: Add .svf output file so CMake can generate data for firmware.
2016-07-10 15:01:04 -07:00
Jared Boone
1cd5a1676c
Ignore all CPLD output_files/ except *.svf.
2016-07-10 15:00:34 -07:00
Jared Boone
805442d46f
Allow KiCad to update metadata.
2015-09-01 11:10:50 -07:00
Jared Boone
d9568f7f47
Update date code to 20150901.
2015-09-01 11:09:19 -07:00
Jared Boone
1c2b3b82ce
Update layers exported during PCB plot.
2015-09-01 10:17:30 -07:00
Jared Boone
73e9dabf72
Change default layer visibility.
2015-09-01 10:14:36 -07:00
Jared Boone
f3f5a9647b
Board stack-up drawing clean-up.
2015-09-01 10:13:51 -07:00
Jared Boone
e979b9b64d
Change drawing lines width to 0.1mm.
2015-09-01 10:02:07 -07:00
Jared Boone
968ec6d176
Change PCB stack-up for vendor.
2015-09-01 10:01:39 -07:00
Jared Boone
128dda23bb
Note about separate PTH and NPTH drill files.
2015-08-30 17:23:53 -07:00
Jared Boone
85f9b4cdc5
Add default dimension units note.
2015-08-30 17:18:14 -07:00
Jared Boone
c5cd3a4498
Add title block with copyright, license.
2015-08-30 17:12:32 -07:00
Jared Boone
d2436ca229
Add notes block.
2015-08-30 17:11:59 -07:00
Jared Boone
18b272bcab
Add PCB dimensions
2015-08-30 16:24:07 -07:00
Jared Boone
d3acd79df8
Add PCB stack data and diagram.
2015-08-30 16:23:55 -07:00
Jared Boone
375cf6f238
Tighten solder mask around LCD connector.
...
Shooting for 4mil mask web between pads.
2015-08-30 14:35:04 -07:00
Jared Boone
84b92365f9
Move and shrink copper layer legend.
...
Doesn't need to be visible after assembly. I think.
2015-08-30 10:14:36 -07:00
Jared Boone
ea2cfb7ad2
Center text in layer legend.
2015-08-30 09:42:47 -07:00
Jared Boone
732561d01c
Change vias to 13mil, 7mil annular ring.
...
Was 13.5mm, but why?!?
2015-08-29 22:31:29 -07:00
Jared Boone
1340991dba
Reduce solder mask margin on WM8731.
...
Trying to squeeze some mask web in there!
2015-08-29 18:14:23 -07:00
Jared Boone
56c7c31cbb
More footprint units cleanup.
2015-08-29 17:54:26 -07:00
Jared Boone
bda376df4b
KiCad added courtyard layers.
2015-08-29 17:20:41 -07:00
Jared Boone
436e6fd21b
Footprint cleanup
...
Remove courtyard lines from silkscreen.
Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units).
Restore U3 refdes silkscreen visibility.
2015-08-29 17:14:06 -07:00
Jared Boone
c78b7fe196
Reduce mask margin on QFP pads.
2015-08-29 16:12:45 -07:00
Jared Boone
d61f3802cb
Remove line in/out components and traces, microphone.
...
Clean up traces and via stitching affected by removed components.
2015-08-27 16:54:38 -07:00
Jared Boone
29243a5fd1
Schematic and netlist from schematic modifications.
2015-08-27 16:54:38 -07:00
Jared Boone
70d7ecc51b
Clean up PCB net labels to match code, CPLD.
2015-08-27 16:54:38 -07:00
Jared Boone
75d9aa9c73
Remove extra CPLD code internal signals.
2015-08-27 16:54:38 -07:00
Jared Boone
19764ce693
Swap function of P2_8, P2_4 in schematic, firmware, CPLD.
...
gpio_unused: P2_4 -> P2_8
gpio_lcd_rd: P2_8 -> P2_4
P2_8 is a very long line, shared with DFU button.
Revise schematic to match CPLD signal names.
2015-08-27 16:54:38 -07:00
Jared Boone
b6e25692dc
Label 1V8 regulator bypass/adjust capacitor as DNI.
...
Was already DNI in assembly BOM. TCR2EF shows that pin as NC.
2015-08-27 16:54:38 -07:00
Jared Boone
1ca4f45d9e
Change VBAT capacitor to DNI.
...
HackRF One has 100nF capacitor on VBAT. Having 10uF capacitor on PortaPack VBAT may slowly drain the coin cell when in storage, and add a bit of leakage current when installed.
2015-08-27 16:54:38 -07:00
Jared Boone
8dfd68a6b3
Removed electret microphone.
2015-08-27 16:54:37 -07:00
Jared Boone
cd4840f1f9
Remove line in/out circuitry.
2015-08-27 16:54:37 -07:00
Jared Boone
84ffaaef33
Back-annotate CVPCB data into schematic.
...
Remove CVPCB .cmp file, since it's a deprecated by the KiCad project.
2015-08-27 16:54:37 -07:00
Jared Boone
bf4521bf35
Update schematic issue/copyright date.
...
KiCad also made some automatic tweaks for latest build (bzr 6109).
2015-08-27 16:54:37 -07:00
Jared Boone
fcec6d6100
OpenSCAD version of case.
...
Minor changes were made between this version and the final version. This earlier version is available via Shapeways, at https://www.shapeways.com/product/EGG3EWPAY/portapack-h1-case-round-20150410-0945
Addresses issue #30 .
2015-08-01 22:27:08 -07:00
Jared Boone
565ea41e92
Hardware gitignore
2015-07-16 10:01:19 -07:00
Jared Boone
604389f8cd
Initial release of schematic, PCB, CPLD code.
2015-07-16 09:54:15 -07:00
