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Add default dimension units note.

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Jared Boone 2015-08-30 17:18:14 -07:00
parent c5cd3a4498
commit 85f9b4cdc5
1 changed files with 3 additions and 0 deletions
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hardware/portapack_h1/portapack_h1.kicad_pcb
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@ -2629,6 +2629,9 @@
(net 63 GND) (solder_mask_margin 0.0762) (solder_paste_margin_ratio -0.1))
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(gr_text "Dimensions in inches, unless otherwise specified." (at 205 168) (layer Dwgs.User)
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(gr_text "Notes, unless otherwise specified:\n\n1. Corner radii, inside: .047 min, unless otherwise stated.\n Corner radii, outside: break all sharp edges and corners.\n\n2. Tolerances:\n Warpage: .010/inch max along longest diag.\n Etching: +/-20% of master pattern.\n\n PTH hole diameter:\n < .100 +/- .003\n > .100 +/- .005\n < .016 + .003, -(hole diameter)\n NPTH hole diameter:\n < .100 +/- .002\n > .100 +/- .003\n\n Front-to-back reg: .005 max.\n (Do not use top-to-bottom pad alignment.)\n Hole plating: .001 min, .003 max.\n Hole diameters are finished sizes.\n\n3. Material: glass-epoxy resin sheet. Refer to board\n stackup for weight of Cu. 2 sides, flame-retardant.\n NEMA grade high temp FR4, TG requirement >= 170C.\n\n4. Finish: Soldermask over bare copper using LPI mask.\n Mask thickness: .0004 min, .0013 max.\n Color: Black\n\n5. Silkscreen legend to board using non-conductive,\n epoxy paint. Remove silkscreen from pads.\n Color: White\n\n6. Acceptability based on IPC-A-600 class 2 (latest revision).\n\n7. Test all boards for opens and shorts.\n\n8. No silkscreen on pads or test points.\n\n9. Do not block mask fine pitch SMD pads.\n\n10. No solder mask on fiducials.\n\n11. No solder mask may cover any gold fingers, if applicable.\n\n12. Do not use top-to-bottom pad alignment.\n Via alignment is recommended.\n\n13. Do not modify solder mask via flooding design.\n Do not modify solder mask chimney designs for test points.\n\n14. No Gerber modifications allowed without prior written\n approval, except for impedance trace width modifications\n to meet requirements, and the addition of tear drops where\n required.\n\n15. Raw material and finished PCB must be RoHS-compliant." (at 200 90) (layer Dwgs.User)
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