Commit Graph

65 Commits

Author SHA1 Message Date
Maescool
920b98f7c9 Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.

* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.

* Schematic: Update power net labels.

* Schematic: Update footprint names to match library changes.

* Schematic: Update header vendor and part numbers.

* Schematic: Specify (arbitrary) value for PDN# net.

* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.

* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.

* Schematic: Update copyright year.

* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.

* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.

* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...

* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.

* PCB: Update copyright on drawing.

* Update schematic and PCB date and revision.

* gitignore: Sublime Text editor project/workspace files

* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...

* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.

* LPC43xx: Add CGU IDIVx struct/union type.

* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.

* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)

* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.

* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.

* MAX V CPLD: Reverse verify data checking logic to make it a little faster.

* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.

* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.

* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...

* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.

* CPLD: Add pins and logic for new PortaPack hardware feature(s).

* CPLD: Bitstream to support new hardware features.

* Clock Generator: Add a couple more setter methods for ClockControl registers.

* Clock Manager: Use shared MCU CLKIN clock control configuration constant.

* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.

* Clock Manager: Remove redundant clock generator output enable.

* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.

* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.

* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.

* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.

* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.

* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.

* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...

* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.

* PortaPack IO: Expose method to set reference oscillator enable pin.

* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.

* Pin configuration: Disable input buffers on pins that are never read.

* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."

This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.

* Remove unused board files.

* Add LPC43xx functions.

* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.

* LPC43xx: Add MCPWM peripheral struct.

* clock generator: Use recommended PLL reset register value.

Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.

* GPIO: Tweak masking of SCU function.

I don't remember why I thought this was necessary...

* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.

* SCU: Add struct to hold pin configuration.

* PAL: Add functions to address The Glitch.

https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/

* PAL/board: New IO initialization code

Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.

* Merge M0 and M4 to eliminate need for bootstrap firmware

During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.

* Pins: Miscellaneous SCU configuration tweaks.

* Little code clarity improvement.

* bootstrap: Remove, not necessary.

* Clock Manager: Large re-working to support external references.

* Fix merge conflicts
2019-01-11 06:56:21 +00:00
Jared Boone
1eb6f10fa6 CPLD: Finish the job of renaming MCU_LCD_(RD|WR).
Caused issue #114, presumably due to RDX being assigned to an unused pin, which was pulled high, and was therefore never asserted.
2017-08-11 14:59:48 -07:00
Jared Boone
8916550e9e CPLD: Enable PCI_IO clamp, unnecessary for LCD_BACKLIGHT signal. 2017-07-20 16:35:17 -07:00
Jared Boone
751ae92509 CPLD: Switch sense of LCD_RD/WR pins.
Should keep CPLD settled when in HackRF mode.
2017-07-20 16:33:55 -07:00
Jared Boone
8bc878c5e5 CPLD: Update 20150901 bitstream due to Makefile changes.
Not sure if any changes have actual significance, but...
2017-07-18 22:08:49 -07:00
Jared Boone
f4744e651b CPLD: Match 20150901 constraints to newer project. 2017-07-17 16:50:26 -07:00
Jared Boone
96c77252c1 Hardware: PCB layout for revision 20170522. 2017-06-19 16:31:54 -07:00
Jared Boone
259348259b Hardware: Schematic for PP H1 revision 20170522. 2017-06-19 16:31:54 -07:00
Jared Boone
1668d4ff7a Case: Make clearances on all sides of PCB into separate variables. 2017-06-19 16:31:54 -07:00
Jared Boone
b0f411f8a4 Case: Separate LED drill diameter into a "parameters" file variable. 2017-06-19 16:31:54 -07:00
Jared Boone
0117962a51 Case: Change board outline to add buffer for H1 LED diffuser. 2017-06-19 16:31:54 -07:00
Jared Boone
626835297b Case: Remove extra mounting hole from PortaPack model. 2017-06-19 16:31:54 -07:00
Jared Boone
a14f764665 CPLD: Update LCD thickness, expected lid thickness to 3/16".
Objective is to keep LCD face below plane of case top/lid.
2017-06-19 16:31:54 -07:00
Jared Boone
8b10fde116 Case: Update spacer height. 2017-06-19 16:31:54 -07:00
Jared Boone
3e8a3d8b9a Case: Clean up boss drills. 2017-06-19 16:31:54 -07:00
Jared Boone
b0b027d557 Case: Adjust feet emboss to match manufactured units. 2017-06-19 16:31:54 -07:00
Jared Boone
023a68ba1d Case: Remove two bosses in center and along side of PCB. 2017-06-19 16:31:54 -07:00
Jared Boone
f4fdc21c20 PCB: Remove series resistors.
Not sure they're of much benefit.
2017-06-19 16:31:54 -07:00
Jared Boone
d1517702b7 PCB: Remove H1 (fifth hole). 2017-06-19 16:31:54 -07:00
Jared Boone
492a704e91 PCB: Interim revision number/date. 2017-06-19 16:31:54 -07:00
Jared Boone
b3c21c3762 CPLD: Ask Quartus to use maximum number of processors. 2017-06-13 21:21:25 -07:00
Jared Boone
9a0fa128c0 CPLD: Clean up *.qws files. 2017-06-13 21:20:19 -07:00
Jared Boone
76c2cc77af CPLD: Move around some .gitignores. 2017-06-01 15:20:16 -07:00
Jared Boone
797e63a590 CPLD: Use correct bitstream for updating hardware.
Determine hardware version and use one of two CPLD bitstream files.
2017-05-31 22:28:07 -07:00
Jared Boone
73d62367d1 CPLD: Makefiles for both hardware variants. 2017-05-31 21:05:47 -07:00
Jared Boone
7c715ed913 CPLD: HDL for 20170522 hardware variant. 2017-05-31 15:21:25 -07:00
Jared Boone
0fd52a7483 CPLD: Move HDL project to hardware revision-specific directory. 2017-05-31 11:50:59 -07:00
Jared Boone
2add96d42d CPLD: Add .svf output file so CMake can generate data for firmware. 2016-07-10 15:01:04 -07:00
Jared Boone
1cd5a1676c Ignore all CPLD output_files/ except *.svf. 2016-07-10 15:00:34 -07:00
Jared Boone
805442d46f Allow KiCad to update metadata. 2015-09-01 11:10:50 -07:00
Jared Boone
d9568f7f47 Update date code to 20150901. 2015-09-01 11:09:19 -07:00
Jared Boone
1c2b3b82ce Update layers exported during PCB plot. 2015-09-01 10:17:30 -07:00
Jared Boone
73e9dabf72 Change default layer visibility. 2015-09-01 10:14:36 -07:00
Jared Boone
f3f5a9647b Board stack-up drawing clean-up. 2015-09-01 10:13:51 -07:00
Jared Boone
e979b9b64d Change drawing lines width to 0.1mm. 2015-09-01 10:02:07 -07:00
Jared Boone
968ec6d176 Change PCB stack-up for vendor. 2015-09-01 10:01:39 -07:00
Jared Boone
128dda23bb Note about separate PTH and NPTH drill files. 2015-08-30 17:23:53 -07:00
Jared Boone
85f9b4cdc5 Add default dimension units note. 2015-08-30 17:18:14 -07:00
Jared Boone
c5cd3a4498 Add title block with copyright, license. 2015-08-30 17:12:32 -07:00
Jared Boone
d2436ca229 Add notes block. 2015-08-30 17:11:59 -07:00
Jared Boone
18b272bcab Add PCB dimensions 2015-08-30 16:24:07 -07:00
Jared Boone
d3acd79df8 Add PCB stack data and diagram. 2015-08-30 16:23:55 -07:00
Jared Boone
375cf6f238 Tighten solder mask around LCD connector.
Shooting for 4mil mask web between pads.
2015-08-30 14:35:04 -07:00
Jared Boone
84b92365f9 Move and shrink copper layer legend.
Doesn't need to be visible after assembly. I think.
2015-08-30 10:14:36 -07:00
Jared Boone
ea2cfb7ad2 Center text in layer legend. 2015-08-30 09:42:47 -07:00
Jared Boone
732561d01c Change vias to 13mil, 7mil annular ring.
Was 13.5mm, but why?!?
2015-08-29 22:31:29 -07:00
Jared Boone
1340991dba Reduce solder mask margin on WM8731.
Trying to squeeze some mask web in there!
2015-08-29 18:14:23 -07:00
Jared Boone
56c7c31cbb More footprint units cleanup. 2015-08-29 17:54:26 -07:00
Jared Boone
bda376df4b KiCad added courtyard layers. 2015-08-29 17:20:41 -07:00
Jared Boone
436e6fd21b Footprint cleanup
Remove courtyard lines from silkscreen.
Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units).
Restore U3 refdes silkscreen visibility.
2015-08-29 17:14:06 -07:00