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CPLD: Match 20150901 constraints to newer project.

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This commit is contained in:
Jared Boone 2017-07-17 16:50:26 -07:00
parent 62b1a82b6b
commit f4744e651b
1 changed files with 3 additions and 3 deletions
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6
hardware/portapack_h1/cpld/20150901/portapack_h1_cpld.sdc
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@ -45,7 +45,7 @@ set lcd_data_wr_hold 10.0
# Create Clock
#**************************************************************
create_clock -name {MCU_STROBE} -period 66.000 -waveform { 0.000 33.000 } [get_ports {MCU_STROBE}]
create_clock -name {MCU_LCD_WR} -period 66.000 -waveform { 0.000 33.000 } [get_ports {MCU_LCD_WR}]
#create_clock -name strobe_virt -period 66.000
#**************************************************************
@ -88,8 +88,8 @@ create_clock -name {MCU_STROBE} -period 66.000 -waveform { 0.000 33.000 } [get_p
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {MCU_STROBE}] -to [get_ports {TP_D TP_L TP_R TP_U}]
set_false_path -from [get_ports {SW_D SW_L SW_R SW_ROT_A SW_ROT_B SW_SEL SW_U}] -to [get_ports {MCU_D[*]}]
#set_false_path -from [get_clocks {MCU_IO_STBX}] -to [get_ports {TP_D TP_L TP_R TP_U}]
#set_false_path -from [get_ports {SW_D SW_L SW_R SW_ROT_A SW_ROT_B SW_SEL SW_U}] -to [get_ports {MCU_D[*]}]
#**************************************************************