2014-12-18 23:45:36 +01:00
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#include "util/constants.h"
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2014-12-03 01:10:06 +01:00
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#ifndef DEVICE_CONFIGURATION
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#define DEVICE_CONFIGURATION
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2019-02-08 13:18:49 +01:00
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// Version info
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#define MAJ_VERSION 0x01
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#define MIN_VERSION 0x00
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2014-12-03 01:10:06 +01:00
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// CPU settings
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2018-12-27 20:24:21 +01:00
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#define TARGET_CPU m1284p
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2019-01-01 20:34:02 +01:00
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#define F_CPU 20000000UL
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2014-12-03 01:10:06 +01:00
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#define FREQUENCY_CORRECTION 0
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2019-01-04 16:13:29 +01:00
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// Voltage references
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2019-02-08 13:18:49 +01:00
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#define CONFIG_ADC_REF 128
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2019-04-05 13:26:53 +02:00
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#define CONFIG_DAC_REF 255
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2019-01-04 16:13:29 +01:00
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2019-04-05 13:26:53 +02:00
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#define CONFIG_LED_INTENSITY 192
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2019-01-12 16:30:26 +01:00
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#define CONFIG_COM_LED_TIMEOUT_MS 40
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#define CONFIG_LED_UPDATE_INTERVAL_MS 40
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2019-01-12 15:12:51 +01:00
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2019-01-04 16:13:29 +01:00
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// Demodulator settings
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2018-04-24 15:34:50 +02:00
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#define OPEN_SQUELCH true
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2014-12-18 23:45:36 +01:00
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2014-12-03 01:10:06 +01:00
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// Serial settings
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2014-12-18 23:45:36 +01:00
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#define SERIAL_DEBUG false
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#define TX_MAXWAIT 2UL
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2019-04-05 13:26:53 +02:00
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#define CONFIG_QUEUE_SIZE 6000
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2019-01-08 20:56:58 +01:00
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#define CONFIG_QUEUE_MAX_LENGTH 15
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2019-04-05 13:26:53 +02:00
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#define CONFIG_UART0_BUFFER_SIZE 1536
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2019-02-04 17:02:19 +01:00
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#define CONFIG_UART1_BUFFER_SIZE 128
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2019-01-08 22:24:29 +01:00
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#define CONFIG_SERIAL_TIMEOUT_MS 10
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2019-01-12 16:30:26 +01:00
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#define CONFIG_BENCHMARK_MODE false
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2014-12-03 01:10:06 +01:00
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2018-12-29 15:57:49 +01:00
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// CSMA Settings
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2019-01-05 13:47:46 +01:00
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#define CONFIG_FULL_DUPLEX false // TODO: Actually implement fdx
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2019-02-08 13:18:49 +01:00
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#define CONFIG_CSMA_P_DEFAULT 255
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#define CONFIG_CSMA_SLOTTIME_DEFAULT 20
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2018-12-29 15:57:49 +01:00
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2019-02-08 21:49:16 +01:00
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#define AX25_MIN_FRAME_LEN 4
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2019-02-07 18:36:40 +01:00
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#define AX25_MAX_FRAME_LEN 611
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#define AX25_MAX_PAYLOAD 576
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2019-02-08 21:49:16 +01:00
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#define AX25_MIN_PAYLOAD 2
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#define AX25_ENCRYPTED_MIN_LENGTH 51 // Padding byte + IV + 1 Block + HMAC + CRC
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2019-01-08 20:56:58 +01:00
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2018-12-30 00:32:19 +01:00
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// Packet settings
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#define CONFIG_PASSALL false
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2014-12-03 01:10:06 +01:00
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// Port settings
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2018-12-27 20:24:21 +01:00
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#if TARGET_CPU == m1284p
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2019-01-27 20:25:11 +01:00
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#define ADC_PORT PORTA
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#define ADC_DDR DDRA
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#define DAC_PORT PORTC
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#define DAC_DDR DDRC
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#define VREF_PORT PORTD
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#define VREF_DDR DDRD
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#define LED_PORT PORTB
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#define LED_DDR DDRB
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#define PTT_DDR DDRD
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#define PTT_PORT PORTD
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#define PTT_PIN 5
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#define PTT_NEG_PIN 4
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#define SPI_PORT PORTB
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#define SPI_DDR DDRB
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#define SPI_MOSI 5
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#define SPI_MISO 6
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#define SPI_CLK 7
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#define SD_CS_DDR DDRA
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#define SD_CS_PORT PORTA
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#define SD_CS_PIN 6
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#define SD_DETECT_DDR DDRA
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#define SD_DETECT_PORT PORTA
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#define SD_DETECT_INPUT PINA
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#define SD_DETECT_PIN 7
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2019-01-29 16:41:27 +01:00
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#define BT_DDR DDRA
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#define BT_PORT PORTA
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#define BT_INPUT PINA
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#define BT_MODE 3
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#define BT_RTS 4
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2019-02-04 17:02:19 +01:00
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#define GPS_DDR DDRA
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#define GPS_PORT PORTA
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#define GPS_INPUT PINA
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#define GPS_EN_PIN 5
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2019-01-29 16:41:27 +01:00
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#define USR_IO_DDR DDRA
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#define USR_IO_PORT PORTA
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#define USR_IO_1 1
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#define USR_IO_2 2
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#define USR_IO_3 3
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#define USR_IO_4 4
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2019-01-12 15:12:51 +01:00
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#endif
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2019-04-05 13:26:53 +02:00
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#endif
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