Joachim Strömbergson f6fa5ae2f9 FPGA: Add CPU instruction address SPI access control ... Add logic that checks if the CPU is reading an instruction to execute from ROM or not. If instructions are read from ROM, access to the SPI from the API is granted, and signals between the SPI master and a slave are allowed. If instructions are not read from ROM, any API access is blocked. and between the SPI master and a slave are disabled. Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-08-22 10:59:27 +02:00
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picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
timer	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
tk1	FPGA: Add CPU instruction address SPI access control	2024-08-22 10:59:27 +02:00
touch_sense	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
trng	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uart	FPGA: Increase clock frequency to 21 MHz	2024-08-20 13:45:00 +02:00
uds	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00