Joachim Strömbergson f6fa5ae2f9 FPGA: Add CPU instruction address SPI access control ... Add logic that checks if the CPU is reading an instruction to execute from ROM or not. If instructions are read from ROM, access to the SPI from the API is granted, and signals between the SPI master and a slave are allowed. If instructions are not read from ROM, any API access is blocked. and between the SPI master and a slave are disabled. Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-08-22 10:59:27 +02:00
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core	FPGA: Add CPU instruction address SPI access control	2024-08-22 10:59:27 +02:00
data	A construction of a minimal SPI master.	2024-06-11 15:28:29 +02:00
fw	FPGA: Add system reset API	2024-08-20 13:25:22 +02:00
rtl	FPGA: Increase clock frequency to 21 MHz	2024-08-20 13:45:00 +02:00
tb	Rename to TK1	2022-10-26 09:20:02 +02:00
tools	hw/tool: UDI/UDS storage	2024-04-03 11:27:00 +02:00
application_fpga.bin.sha256	FPGA: Increase clock frequency to 21 MHz	2024-08-20 13:45:00 +02:00
config.vlt	Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal	2023-03-01 13:37:31 +01:00
firmware.bin.sha512	FPGA: Update names for RAM randomization API	2024-07-10 13:45:26 +02:00
Makefile	FPGA: Add --freq constraint to nextpnr	2024-08-20 13:45:01 +02:00